SuccessChanges

Summary

  1. [llvm-mca] Remove redundant namespace prefixes. NFC We are already "using" namespace llvm in all the files modified by this change.
  2. [X86][Btver2] Fix BSF/BSR schedule Double throughput to account for 2 pipes + fix BSF's latency/uop counts Match AMD Fam16h SOG + llvm-exegesis tests
  3. Revert r343308: [LoopInterchange] Turn into a loop pass.
  4. [LoopInterchange] Turn into a loop pass. This patch turns LoopInterchange into a loop pass. It now only considers top-level loops and tries to move the innermost loop to the optimal position within the loop nest. By only looking at top-level loops, we might miss a few opportunities the function pass would get (e.g. if we have a loop nest of 3 loops, in the function pass we might process loops at level 1 and 2 and move the inner most loop to level 1, and then we process loops at levels 0, 1, 2 and interchange again, because we now have a different inner loop). But I think it would be better to handle such cases by picking the best inner loop from the start and avoid re-visiting the same loops again. The biggest advantage of it being a function pass is that it interacts nicely with the other loop passes. Without this patch, there are some performance regressions on AArch64 with loop interchanging enabled, where no loops were interchanged, but we missed out on some other loop optimizations. It also removes the SimplifyCFG run. We are just changing branches, so the CFG should not be more complicated, besides the additional 'unique' preheaders this pass might create. Reviewers: chandlerc, efriedma, mcrosier, javed.absar, xbolva00 Reviewed By: xbolva00 Differential Revision: https://reviews.llvm.org/D51702
  5. [llvm-mca] Teach how to track zero registers in class RegisterFile. This change is in preparation for a future work on improving support for optimizable register moves. We already know if a write is from a zero-idiom, so we can propagate that bit of information to the PRF. We use an APInt mask to identify registers that are set to zero.
Revision 343312 by adibiagio:
[llvm-mca] Remove redundant namespace prefixes. NFC

We are already "using" namespace llvm in all the files modified by this change.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpptrunk/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp
The file was modified/llvm/trunk/tools/llvm-mca/lib/HardwareUnits/ResourceManager.cpptrunk/tools/llvm-mca/lib/HardwareUnits/ResourceManager.cpp
The file was modified/llvm/trunk/tools/llvm-mca/lib/HardwareUnits/RetireControlUnit.cpptrunk/tools/llvm-mca/lib/HardwareUnits/RetireControlUnit.cpp
The file was modified/llvm/trunk/tools/llvm-mca/lib/InstrBuilder.cpptrunk/tools/llvm-mca/lib/InstrBuilder.cpp
The file was modified/llvm/trunk/tools/llvm-mca/lib/Instruction.cpptrunk/tools/llvm-mca/lib/Instruction.cpp
The file was modified/llvm/trunk/tools/llvm-mca/lib/Pipeline.cpptrunk/tools/llvm-mca/lib/Pipeline.cpp
The file was modified/llvm/trunk/tools/llvm-mca/lib/Stages/DispatchStage.cpptrunk/tools/llvm-mca/lib/Stages/DispatchStage.cpp
The file was modified/llvm/trunk/tools/llvm-mca/lib/Stages/ExecuteStage.cpptrunk/tools/llvm-mca/lib/Stages/ExecuteStage.cpp
Revision 343311 by rksimon:
[X86][Btver2] Fix BSF/BSR schedule

Double throughput to account for 2 pipes + fix BSF's latency/uop counts

Match AMD Fam16h SOG + llvm-exegesis tests
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.tdtrunk/lib/Target/X86/X86ScheduleBtVer2.td
The file was modified/llvm/trunk/test/CodeGen/X86/schedule-x86_64.lltrunk/test/CodeGen/X86/schedule-x86_64.ll
The file was modified/llvm/trunk/test/tools/llvm-mca/X86/BtVer2/clear-super-register-1.strunk/test/tools/llvm-mca/X86/BtVer2/clear-super-register-1.s
The file was modified/llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.strunk/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s
Revision 343310 by fhahn:
Revert r343308: [LoopInterchange] Turn into a loop pass.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/IPO/PassManagerBuilder.cpptrunk/lib/Transforms/IPO/PassManagerBuilder.cpp
The file was modified/llvm/trunk/lib/Transforms/Scalar/LoopInterchange.cpptrunk/lib/Transforms/Scalar/LoopInterchange.cpp
Revision 343308 by fhahn:
[LoopInterchange] Turn into a loop pass.

This patch turns LoopInterchange into a loop pass. It now only
considers top-level loops and tries to move the innermost loop to the
optimal position within the loop nest. By only looking at top-level
loops, we might miss a few opportunities the function pass would get
(e.g. if we have a loop nest of 3 loops, in the function pass
we might process loops at level 1 and 2 and move the inner most loop to
level 1, and then we process loops at levels 0, 1, 2 and interchange
again, because we now have a different inner loop). But I think it would
be better to handle such cases by picking the best inner loop from the
start and avoid re-visiting the same loops again.

The biggest advantage of it being a function pass is that it interacts
nicely with the other loop passes. Without this patch, there are some
performance regressions on AArch64 with loop interchanging enabled,
where no loops were interchanged, but we missed out on some other loop
optimizations.

It also removes the SimplifyCFG run. We are just changing branches, so
the CFG should not be more complicated, besides the additional 'unique'
preheaders this pass might create.


Reviewers: chandlerc, efriedma, mcrosier, javed.absar, xbolva00

Reviewed By: xbolva00

Differential Revision: https://reviews.llvm.org/D51702
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/IPO/PassManagerBuilder.cpptrunk/lib/Transforms/IPO/PassManagerBuilder.cpp
The file was modified/llvm/trunk/lib/Transforms/Scalar/LoopInterchange.cpptrunk/lib/Transforms/Scalar/LoopInterchange.cpp
Revision 343307 by adibiagio:
[llvm-mca] Teach how to track zero registers in class RegisterFile.

This change is in preparation for a future work on improving support for
optimizable register moves.  We already know if a write is from a zero-idiom, so
we can propagate that bit of information to the PRF.  We use an APInt mask to
identify registers that are set to zero.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/tools/llvm-mca/include/HardwareUnits/RegisterFile.htrunk/tools/llvm-mca/include/HardwareUnits/RegisterFile.h
The file was modified/llvm/trunk/tools/llvm-mca/include/Instruction.htrunk/tools/llvm-mca/include/Instruction.h
The file was modified/llvm/trunk/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpptrunk/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp

Summary

  1. [ARM] Prevent DSP and SIM32 being set for v6m My previous change (rL340911) set the two features for architectures >= 6, which wrongly includes v6m. Now set to >= 6 and not Cortex-M. Differential Revision: https://reviews.llvm.org/D52644
  2. [ClangFormat] 'try' of function-try-block doesn't obey BraceWrapping It should respond to AfterFunction, not AfterControlStatement. Fixes PR39067
  3. [ARM] Alter test to account for change to armv6k default CPU Review D52594 will change the default in llvm for armv6k from the non-existent cpu arm1176jf-s to mpcore. The tests in arm-cortex-cpus.c need to be updated to account for this change. Differential Revision: https://reviews.llvm.org/D52595
Revision 343309 by sam_parker:
[ARM] Prevent DSP and SIM32 being set for v6m

My previous change (rL340911) set the two features for architectures
>= 6, which wrongly includes v6m. Now set to >= 6 and not Cortex-M.

Differential Revision: https://reviews.llvm.org/D52644
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/lib/Basic/Targets/ARM.cpptrunk/lib/Basic/Targets/ARM.cpp
The file was modified/cfe/trunk/test/Preprocessor/arm-acle-6.4.ctrunk/test/Preprocessor/arm-acle-6.4.c
Revision 343305 by owenpan:
[ClangFormat] 'try' of function-try-block doesn't obey BraceWrapping

It should respond to AfterFunction, not AfterControlStatement.

Fixes PR39067
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/lib/Format/UnwrappedLineParser.cpptrunk/lib/Format/UnwrappedLineParser.cpp
The file was modified/cfe/trunk/unittests/Format/FormatTest.cpptrunk/unittests/Format/FormatTest.cpp
Revision 343304 by psmith:
[ARM] Alter test to account for change to armv6k default CPU

Review D52594 will change the default in llvm for armv6k from the
non-existent cpu arm1176jf-s to mpcore. The tests in arm-cortex-cpus.c
need to be updated to account for this change.

Differential Revision: https://reviews.llvm.org/D52595
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/test/Driver/arm-cortex-cpus.ctrunk/test/Driver/arm-cortex-cpus.c

Summary

  1. [docs] Fix links in Clangd documentation Add missing `_` after each `external link <https://llvm.org>`_, as required by the reStructuredText specification.
Revision 343306 by omtcyfz:
[docs] Fix links in Clangd documentation

Add missing `_` after each `external link <https://llvm.org>`_, as
required by the reStructuredText specification.
Change TypePath in RepositoryPath in Workspace
The file was modified/clang-tools-extra/trunk/docs/clangd.rsttrunk/docs/clangd.rst