SuccessChanges

Summary

  1. AMDGPU/GlobalISel: Handle llvm.amdgcn.if.break
  2. AMDGPU: Remove reserved value accidentally left in for gfx908
  3. AMDGPU/GlobalISel: Select llvm.amdgcn.end.cf
  4. [x86] try to keep FP casted+truncated+extracted vector element out of GPRs inttofp (trunc (extelt X, 0)) --> inttofp (extelt (bitcast X), 0) We have pseudo-vectorization of scalar int to FP casts, so this tries to make that more likely by replacing a truncate with a bitcast. I didn't see any test diffs starting from 'uitofp', so I left that as a TODO. We can't only match the shorter trunc+extract pattern because there's an opposing transform somewhere, so we infinite loop. Waiting to try this during lowering is another possibility. A motivating case is shown in PR39975 and included in the test diffs here: https://bugs.llvm.org/show_bug.cgi?id=39975 Differential Revision: https://reviews.llvm.org/D64710
Revision 366102 by arsenm:
AMDGPU/GlobalISel: Handle llvm.amdgcn.if.break
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (diff)llvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (diff)llvm.src/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.llllvm.src/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.llllvm.src/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
Revision 366101 by kzhuravl:
AMDGPU: Remove reserved value accidentally left in for gfx908
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/BinaryFormat/ELF.h (diff)llvm.src/include/llvm/BinaryFormat/ELF.h
Revision 366099 by arsenm:
AMDGPU/GlobalISel: Select llvm.amdgcn.end.cf
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (diff)llvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (diff)llvm.src/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.llllvm.src/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.llllvm.src/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
Revision 366098 by spatel:
[x86] try to keep FP casted+truncated+extracted vector element out of GPRs

inttofp (trunc (extelt X, 0)) --> inttofp (extelt (bitcast X), 0)

We have pseudo-vectorization of scalar int to FP casts, so this tries to
make that more likely by replacing a truncate with a bitcast. I didn't see
any test diffs starting from 'uitofp', so I left that as a TODO. We can't
only match the shorter trunc+extract pattern because there's an opposing
transform somewhere, so we infinite loop. Waiting to try this during
lowering is another possibility.

A motivating case is shown in PR39975 and included in the test diffs here:
https://bugs.llvm.org/show_bug.cgi?id=39975

Differential Revision: https://reviews.llvm.org/D64710
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (diff)llvm.src/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/known-bits-vector.ll (diff)llvm.src/test/CodeGen/X86/known-bits-vector.ll
The file was modified/llvm/trunk/test/CodeGen/X86/known-signbits-vector.ll (diff)llvm.src/test/CodeGen/X86/known-signbits-vector.ll