SuccessChanges

Summary

  1. AMDGPU/GlobalISel: Select G_AND/G_OR/G_XOR
  2. AMDGPU/GlobalISel: Don't constrain source register of VCC copies This is a hack until I come up with a better way of dealing with the pseudo-register banks used for boolean values. If the use instruction constrains the register, the selector for the def instruction won't see that the bank was VCC. A 1-bit SReg_32 is could ambiguously have been SCCRegBank or VCCRegBank in wave32. This is necessary to successfully select branches with and and/or/xor condition.
  3. AMDGPU/GlobalISel: Fix selecting vcc->vcc bank copies The extra test change is correct, although how it arrives there is a bug that needs work. With wave32, the test for isVCC ambiguously reports true for an SCC or VCC source. A new allocatable pseudo register class for SCC may be necesssary.
  4. AMDGPU/GlobalISel: Fix not constraining result reg of copies to VCC
Revision 366121 by arsenm:
AMDGPU/GlobalISel: Select G_AND/G_OR/G_XOR
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (diff)llvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h (diff)llvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
Revision 366120 by arsenm:
AMDGPU/GlobalISel: Don't constrain source register of VCC copies

This is a hack until I come up with a better way of dealing with the
pseudo-register banks used for boolean values. If the use instruction
constrains the register, the selector for the def instruction won't
see that the bank was VCC. A 1-bit SReg_32 is could ambiguously have
been SCCRegBank or VCCRegBank in wave32.

This is necessary to successfully select branches with and and/or/xor
condition.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (diff)llvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
Revision 366119 by arsenm:
AMDGPU/GlobalISel: Fix selecting vcc->vcc bank copies

The extra test change is correct, although how it arrives there is a
bug that needs work. With wave32, the test for isVCC ambiguously
reports true for an SCC or VCC source. A new allocatable pseudo
register class for SCC may be necesssary.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (diff)llvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
Revision 366118 by arsenm:
AMDGPU/GlobalISel: Fix not constraining result reg of copies to VCC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (diff)llvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir