SuccessChanges

Summary

  1. AMDGPU/GlobalISel: Allow scalar s1 and/or/xor If a 1-bit value is in a 32-bit VGPR, the scalar opcodes set SCC to whether the result is 0. If the inputs are SCC, these can be copied to a 32-bit SGPR to produce an SCC result.
Revision 366125 by arsenm:
AMDGPU/GlobalISel: Allow scalar s1 and/or/xor

If a 1-bit value is in a 32-bit VGPR, the scalar opcodes set SCC to
whether the result is 0. If the inputs are SCC, these can be copied to
a 32-bit SGPR to produce an SCC result.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (diff)llvm.src/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir