SuccessChanges

Summary

  1. AMDGPU/GlobalISel: Select G_LSHR
  2. [PowerPC][HTM] Fix impossible reg-to-reg copy assert with ttest builtin Summary: This is exposed by our internal testing. The reduced testcase will assert with "Impossible reg-to-reg copy" We can't use COPY to do 32-bit to 64-bit conversion. Reviewers: kbarton, hfinkel, nemanjai Reviewed By: hfinkel Subscribers: hiraditya, MaskRay, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64499
  3. AMDGPU/GlobalISel: Select G_SHL I think this manages to not break the DAG handling with the divergent predicates because the stadalone divergent patterns end up with a higher priority than the pattern on the instruction definition. The 16-bit versions don't work yet.
Revision 366256 by arsenm:
AMDGPU/GlobalISel: Select G_LSHR
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td (diff)llvm.src/lib/Target/AMDGPU/SOPInstructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td (diff)llvm.src/lib/Target/AMDGPU/VOP2Instructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td (diff)llvm.src/lib/Target/AMDGPU/VOP3Instructions.td
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir
Revision 366255 by jsji:
[PowerPC][HTM] Fix impossible reg-to-reg copy assert with ttest builtin

Summary:
This is exposed by our internal testing.
The reduced testcase will assert with "Impossible reg-to-reg copy"

We can't use COPY to do 32-bit to 64-bit conversion.

Reviewers: kbarton, hfinkel, nemanjai

Reviewed By: hfinkel

Subscribers: hiraditya, MaskRay, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64499
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCInstrHTM.td (diff)llvm.src/lib/Target/PowerPC/PPCInstrHTM.td
The file was added/llvm/trunk/test/CodeGen/PowerPC/htm-ttest.llllvm.src/test/CodeGen/PowerPC/htm-ttest.ll
Revision 366254 by arsenm:
AMDGPU/GlobalISel: Select G_SHL

I think this manages to not break the DAG handling with the divergent
predicates because the stadalone divergent patterns end up with a
higher priority than the pattern on the instruction definition.

The 16-bit versions don't work yet.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td (diff)llvm.src/lib/Target/AMDGPU/SOPInstructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td (diff)llvm.src/lib/Target/AMDGPU/VOP2Instructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td (diff)llvm.src/lib/Target/AMDGPU/VOP3Instructions.td
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir