SuccessChanges

Summary

  1. AMDGPU/GlobalISel: Rewrite lowerFormalArguments This should now handle everything except structs passed as multiple registers. I think most of the packing logic should be handled by handleAssignments, but I'm unclear on what the contract is for multiple registers. This is copying how x86 handles this. This does change the behavior of the test_sgpr_alignment0 amdgpu_vs test. I don't think shader arguments should try to follow the alignment, and registers need to be repacked. I also don't think it matters, since I think the pointers are packed to the beginning of the argument list anyway.
  2. AMDGPU: Decompose all values to 32-bit pieces for calling conventions This is the more natural lowering, and presents more opportunities to reduce 64-bit ops to 32-bit. This should also help avoid issues graphics shaders have had with 64-bit values, and simplify argument lowering in globalisel.
  3. gn build: Set +x on symlink_or_copy.py
  4. DAG: Handle dbg_value for arguments split into multiple subregs This was handled previously for arguments split due to not fitting in an MVT. This was dropping the register for argument registers split due to TLI::getRegisterTypeForCallingConv.
Revision 366582 by arsenm:
AMDGPU/GlobalISel: Rewrite lowerFormalArguments

This should now handle everything except structs passed as multiple
registers.

I think most of the packing logic should be handled by
handleAssignments, but I'm unclear on what the contract is for
multiple registers. This is copying how x86 handles this.

This does change the behavior of the test_sgpr_alignment0 amdgpu_vs
test. I don't think shader arguments should try to follow the
alignment, and registers need to be repacked. I also don't think it
matters, since I think the pointers are packed to the beginning of the
argument list anyway.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.cpp (diff)llvm.src/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.h (diff)llvm.src/lib/Target/AMDGPU/AMDGPUCallLowering.h
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (diff)llvm.src/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h (diff)llvm.src/lib/Target/AMDGPU/SIISelLowering.h
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.llllvm.src/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
Revision 366578 by arsenm:
AMDGPU: Decompose all values to 32-bit pieces for calling conventions

This is the more natural lowering, and presents more opportunities to
reduce 64-bit ops to 32-bit.

This should also help avoid issues graphics shaders have had with
64-bit values, and simplify argument lowering in globalisel.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUCallingConv.td (diff)llvm.src/lib/Target/AMDGPU/AMDGPUCallingConv.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp (diff)llvm.src/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (diff)llvm.src/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/call-argument-types.ll (diff)llvm.src/test/CodeGen/AMDGPU/call-argument-types.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/debug-value2.ll (diff)llvm.src/test/CodeGen/AMDGPU/debug-value2.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/implicit-def-muse.ll (diff)llvm.src/test/CodeGen/AMDGPU/implicit-def-muse.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/reduce-build-vec-ext-to-ext-build-vec.ll (diff)llvm.src/test/CodeGen/AMDGPU/reduce-build-vec-ext-to-ext-build-vec.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/shift-i128.ll (diff)llvm.src/test/CodeGen/AMDGPU/shift-i128.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/si-scheduler.ll (diff)llvm.src/test/CodeGen/AMDGPU/si-scheduler.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/split-arg-dbg-value.ll (diff)llvm.src/test/CodeGen/AMDGPU/split-arg-dbg-value.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/vector_shuffle.packed.ll (diff)llvm.src/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/wait.ll (diff)llvm.src/test/CodeGen/AMDGPU/wait.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/wwm-reserved.ll (diff)llvm.src/test/CodeGen/AMDGPU/wwm-reserved.ll
Revision 366576 by nico:
gn build: Set +x on symlink_or_copy.py
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/utils/gn/build/symlink_or_copy.py (diff)llvm.src/utils/gn/build/symlink_or_copy.py
Revision 366574 by arsenm:
DAG: Handle dbg_value for arguments split into multiple subregs

This was handled previously for arguments split due to not fitting in
an MVT. This was dropping the register for argument registers split
due to TLI::getRegisterTypeForCallingConv.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (diff)llvm.src/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was added/llvm/trunk/test/CodeGen/AMDGPU/split-arg-dbg-value.llllvm.src/test/CodeGen/AMDGPU/split-arg-dbg-value.ll