SuccessChanges

Summary

  1. AMDGPU: Don't rely on m0 being -1 for GWS offsets This only works if the high bits of m0 are also 0, so m0 would have to be set to 0xffff.
Revision 366608 by arsenm:
AMDGPU: Don't rely on m0 being -1 for GWS offsets

This only works if the high bits of m0 are also 0, so m0 would have to
be set to 0xffff.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp (diff)llvm.src/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll (diff)llvm.src/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll (diff)llvm.src/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.br.ll (diff)llvm.src/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.br.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.p.ll (diff)llvm.src/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.p.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll (diff)llvm.src/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.v.ll (diff)llvm.src/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.v.ll