SuccessChanges

Summary

  1. [X86] When using AND+PACKUS in lowerV16I8Shuffle, generate the build vector directly in v16i8 with the correct 0x00 or 0xFF elements rather than using another VT and bitcasting it. The build_vector will become a constant pool load. By using the desired type initially, it ensures we don't generate a bitcast of the constant pool load which will need to be folded with the load. While experimenting with another patch, I noticed that when the load type and the constant pool type don't match, then SimplifyDemandedBits can't handle it. While we should probably fix that, this was a simple way to fix the issue I saw.
  2. [NFC][PowerPC]Change ADDIStocHA to ADDIStocHA8 to follow 64-bit naming convention Summary: Since we are planning to add ADDIStocHA for 32bit in later patch, we decided to change 64bit one first to follow naming convention with 8 behind opcode. Patch by: Xiangling_L Differential Revision: https://reviews.llvm.org/D64814
Revision 366732 by ctopper:
[X86] When using AND+PACKUS in lowerV16I8Shuffle, generate the build vector directly in v16i8 with the correct 0x00 or 0xFF elements rather than using another VT and bitcasting it.

The build_vector will become a constant pool load. By using the
desired type initially, it ensures we don't generate a bitcast
of the constant pool load which will need to be folded with
the load.

While experimenting with another patch, I noticed that when the
load type and the constant pool type don't match, then
SimplifyDemandedBits can't handle it. While we should probably
fix that, this was a simple way to fix the issue I saw.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (diff)llvm.src/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/avg.ll (diff)llvm.src/test/CodeGen/X86/avg.ll
The file was modified/llvm/trunk/test/CodeGen/X86/masked_store_trunc.ll (diff)llvm.src/test/CodeGen/X86/masked_store_trunc.ll
The file was modified/llvm/trunk/test/CodeGen/X86/mmx-arith.ll (diff)llvm.src/test/CodeGen/X86/mmx-arith.ll
The file was modified/llvm/trunk/test/CodeGen/X86/oddshuffles.ll (diff)llvm.src/test/CodeGen/X86/oddshuffles.ll
The file was modified/llvm/trunk/test/CodeGen/X86/oddsubvector.ll (diff)llvm.src/test/CodeGen/X86/oddsubvector.ll
The file was modified/llvm/trunk/test/CodeGen/X86/psubus.ll (diff)llvm.src/test/CodeGen/X86/psubus.ll
The file was modified/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-canonical.ll (diff)llvm.src/test/CodeGen/X86/sse2-intrinsics-canonical.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-reduce-and-bool.ll (diff)llvm.src/test/CodeGen/X86/vector-reduce-and-bool.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-reduce-or-bool.ll (diff)llvm.src/test/CodeGen/X86/vector-reduce-or-bool.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-reduce-xor-bool.ll (diff)llvm.src/test/CodeGen/X86/vector-reduce-xor-bool.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-shuffle-128-v16.ll (diff)llvm.src/test/CodeGen/X86/vector-shuffle-128-v16.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-trunc-math-widen.ll (diff)llvm.src/test/CodeGen/X86/vector-trunc-math-widen.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-trunc-math.ll (diff)llvm.src/test/CodeGen/X86/vector-trunc-math.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-trunc-widen.ll (diff)llvm.src/test/CodeGen/X86/vector-trunc-widen.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-trunc.ll (diff)llvm.src/test/CodeGen/X86/vector-trunc.ll
Revision 366731 by jasonliu:
[NFC][PowerPC]Change ADDIStocHA to ADDIStocHA8 to follow 64-bit naming convention

Summary:

Since we are planning to add ADDIStocHA for 32bit in later patch, we decided
to change 64bit one first to follow naming convention with 8 behind opcode.

Patch by: Xiangling_L

Differential Revision: https://reviews.llvm.org/D64814
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/PowerPC/P9InstrResources.td (diff)llvm.src/lib/Target/PowerPC/P9InstrResources.td
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp (diff)llvm.src/lib/Target/PowerPC/PPCAsmPrinter.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp (diff)llvm.src/lib/Target/PowerPC/PPCFastISel.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (diff)llvm.src/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (diff)llvm.src/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (diff)llvm.src/lib/Target/PowerPC/PPCInstr64Bit.td
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (diff)llvm.src/lib/Target/PowerPC/PPCInstrInfo.cpp
The file was modified/llvm/trunk/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.mir (diff)llvm.src/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.mir
The file was modified/llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir (diff)llvm.src/test/CodeGen/PowerPC/aantidep-def-ec.mir
The file was modified/llvm/trunk/test/CodeGen/PowerPC/licm-tocReg.ll (diff)llvm.src/test/CodeGen/PowerPC/licm-tocReg.ll
The file was modified/llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir (diff)llvm.src/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
The file was modified/llvm/trunk/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir (diff)llvm.src/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir