SuccessChanges

Summary

  1. [GlobalISel][AArch64] Teach GISel to handle shifts in load addressing modes When we select the XRO variants of loads, we can pull in very specific shifts (of the size of an element). E.g. ``` ldr x1, [x2, x3, lsl #3] ``` This teaches GISel to handle these when they're coming from shifts specifically. This adds a new addressing mode function, `selectAddrModeShiftedExtendXReg` which recognizes this pattern. This also packs this up with `selectAddrModeRegisterOffset` into `selectAddrModeXRO`. This is intended to be equivalent to `selectAddrModeXRO` in AArch64ISelDAGtoDAG. Also update load-addressing-modes to show that all of the cases here work. Differential Revision: https://reviews.llvm.org/D65119
  2. [ASTImporter] Fix inequivalence of ClassTemplateInstantiations Summary: We falsely state inequivalence if the template parameter is a qualified/nonquialified template in the first/second instantiation. Also, different kinds of TemplateName should be equal if the template decl (if available) is equal (even if the name kind is different). Reviewers: a_sidorin, a.sidorin Subscribers: rnkovacs, dkrupp, Szelethus, gamesh411, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D64241
  3. [TargetLowering] SimplifyMultipleUseDemandedBits - add VECTOR_SHUFFLE support. If all the demanded elts are from one operand and are inline, then we can use the operand directly. The changes are mainly from SSE41 targets which has blendvpd but not cmpgtq, allowing the v2i64 comparison to be simplified as we only need the signbit from alternate v4i32 elements.
Revision 366819 by paquette:
[GlobalISel][AArch64] Teach GISel to handle shifts in load addressing modes

When we select the XRO variants of loads, we can pull in very specific shifts
(of the size of an element). E.g.

```
ldr x1, [x2, x3, lsl #3]
```

This teaches GISel to handle these when they're coming from shifts
specifically.

This adds a new addressing mode function, `selectAddrModeShiftedExtendXReg`
which recognizes this pattern.

This also packs this up with `selectAddrModeRegisterOffset` into
`selectAddrModeXRO`. This is intended to be equivalent to `selectAddrModeXRO`
in AArch64ISelDAGtoDAG.

Also update load-addressing-modes to show that all of the cases here work.

Differential Revision: https://reviews.llvm.org/D65119
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (diff)llvm.src/lib/Target/AArch64/AArch64InstructionSelector.cpp
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir (diff)llvm.src/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
Revision 366818 by martong:
[ASTImporter] Fix inequivalence of ClassTemplateInstantiations

Summary:
We falsely state inequivalence if the template parameter is a
qualified/nonquialified template in the first/second instantiation.
Also, different kinds of TemplateName should be equal if the template
decl (if available) is equal (even if the name kind is different).

Reviewers: a_sidorin, a.sidorin

Subscribers: rnkovacs, dkrupp, Szelethus, gamesh411, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D64241
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/lib/AST/ASTStructuralEquivalence.cpp (diff)clang.src/lib/AST/ASTStructuralEquivalence.cpp
The file was modified/cfe/trunk/unittests/AST/StructuralEquivalenceTest.cpp (diff)clang.src/unittests/AST/StructuralEquivalenceTest.cpp
Revision 366817 by rksimon:
[TargetLowering] SimplifyMultipleUseDemandedBits - add VECTOR_SHUFFLE support.

If all the demanded elts are from one operand and are inline, then we can use the operand directly.

The changes are mainly from SSE41 targets which has blendvpd but not cmpgtq, allowing the v2i64 comparison to be simplified as we only need the signbit from alternate v4i32 elements.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (diff)llvm.src/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/midpoint-int-vec-128.ll (diff)llvm.src/test/CodeGen/X86/midpoint-int-vec-128.ll
The file was modified/llvm/trunk/test/CodeGen/X86/psubus.ll (diff)llvm.src/test/CodeGen/X86/psubus.ll
The file was modified/llvm/trunk/test/CodeGen/X86/sat-add.ll (diff)llvm.src/test/CodeGen/X86/sat-add.ll
The file was modified/llvm/trunk/test/CodeGen/X86/uadd_sat_vec.ll (diff)llvm.src/test/CodeGen/X86/uadd_sat_vec.ll
The file was modified/llvm/trunk/test/CodeGen/X86/usub_sat_vec.ll (diff)llvm.src/test/CodeGen/X86/usub_sat_vec.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vec_minmax_sint.ll (diff)llvm.src/test/CodeGen/X86/vec_minmax_sint.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vec_minmax_uint.ll (diff)llvm.src/test/CodeGen/X86/vec_minmax_uint.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-fshl-rot-512.ll (diff)llvm.src/test/CodeGen/X86/vector-fshl-rot-512.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-fshr-rot-512.ll (diff)llvm.src/test/CodeGen/X86/vector-fshr-rot-512.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-reduce-smax-widen.ll (diff)llvm.src/test/CodeGen/X86/vector-reduce-smax-widen.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-reduce-smax.ll (diff)llvm.src/test/CodeGen/X86/vector-reduce-smax.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-reduce-smin-widen.ll (diff)llvm.src/test/CodeGen/X86/vector-reduce-smin-widen.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-reduce-smin.ll (diff)llvm.src/test/CodeGen/X86/vector-reduce-smin.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-reduce-umax-widen.ll (diff)llvm.src/test/CodeGen/X86/vector-reduce-umax-widen.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-reduce-umax.ll (diff)llvm.src/test/CodeGen/X86/vector-reduce-umax.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-reduce-umin-widen.ll (diff)llvm.src/test/CodeGen/X86/vector-reduce-umin-widen.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-reduce-umin.ll (diff)llvm.src/test/CodeGen/X86/vector-reduce-umin.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-trunc-packus-widen.ll (diff)llvm.src/test/CodeGen/X86/vector-trunc-packus-widen.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-trunc-packus.ll (diff)llvm.src/test/CodeGen/X86/vector-trunc-packus.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-trunc-ssat-widen.ll (diff)llvm.src/test/CodeGen/X86/vector-trunc-ssat-widen.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-trunc-ssat.ll (diff)llvm.src/test/CodeGen/X86/vector-trunc-ssat.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-trunc-usat-widen.ll (diff)llvm.src/test/CodeGen/X86/vector-trunc-usat-widen.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-trunc-usat.ll (diff)llvm.src/test/CodeGen/X86/vector-trunc-usat.ll