FailedChanges

Changes from Git (git http://labmaster3.local/git/llvm-zorg.git)

Summary

  1. Update URL for last-good-build.properties (details)
  2. Update test suite jobs to use monorepo. (details)
Commit 011d02dc682f0fed450aceeb194e6fd4bff076a6 by Jessica Paquette
Update URL for last-good-build.properties
The last_good_build.properties file is no longer hosted at
http://labmaster2.local/artifacts/clang-stage1-configure-RA
Update it to point to its new home at
http://labmaster2.local/artifacts/clang-stage1-RA
(This might cause some things to break, which were relying on LLVM_REV
being set. Those things were needlessly spinning on the same compiler
though, so they really ought to be broken anyway.)
llvm-svn: 367629
The file was modifiedzorg/jenkins/relay.groovy
Commit 8eeec64eff49df2ce77bd75844fdf3e92faabae5 by Jessica Paquette
Update test suite jobs to use monorepo.
Changes to relevant test generator files:
common.groovy:
- Kill all the SVN stuff and use the monorepo instead.
- Use GIT_SHA/GIT_DISTANCE
relay.groovy:
- Set/use GIT_SHA and GIT_DISTANCE instead of LLVM_REV
llvm-svn: 367630
The file was modifiedzorg/jenkins/relay.groovy
The file was modifiedzorg/jenkins/common.groovy

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. Refactor deque to centralize handling of spare blocks. (details)
  2. [DirectoryWatcher] Relax assumption to prevent test flakiness (details)
  3. Finish moving TargetRegisterInfo::isVirtualRegister() and friends to (details)
  4. [Tests] Autogen a bunch of Reassociate tests for ease of update (details)
  5. [dsymutil] Fix heap-use-after-free related to the LinkOptions. (details)
  6. Prevent vregs leaking into the MC layer via (details)
  7. Fix up an unused variable warning caused by TRI->isVirtualRegister() -> (details)
  8. Format OptionEnumValueElement (NFC) (details)
  9. Update Compiler.h check for MSVC We require at least MSVC 2017, but I (details)
Commit d544d1441d98308eeea98969c3311bbd24fd6b0f by eric
Refactor deque to centralize handling of spare blocks.
I have upcoming changes that modify how deque handles spare blocks. This
cleanup is intended to make those changes easier to review and
understand. This patch should have NFC.
llvm-svn: 367631
The file was addedlibcxx/test/libcxx/containers/sequences/deque/spare_block_handling.pass.cpp
The file was modifiedlibcxx/include/deque
Commit 9debb024d44db54b9453459d3bd98d28c20a163f by Jan Korous
[DirectoryWatcher] Relax assumption to prevent test flakiness
llvm-svn: 367632
The file was modifiedclang/unittests/DirectoryWatcher/DirectoryWatcherTest.cpp
The file was modifiedclang/lib/DirectoryWatcher/mac/DirectoryWatcher-mac.cpp
Commit 2bea69bf6503ffc9f3cde9a52b5dac1a25e94e1c by daniel_l_sanders
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to
llvm::Register as started by r367614. NFC
llvm-svn: 367633
The file was modifiedllvm/lib/CodeGen/MachineSink.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
The file was modifiedllvm/lib/CodeGen/ShrinkWrap.cpp
The file was modifiedllvm/lib/CodeGen/MachineOperand.cpp
The file was modifiedllvm/lib/Target/AMDGPU/GCNRegPressure.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
The file was modifiedllvm/lib/CodeGen/RegAllocFast.cpp
The file was modifiedllvm/lib/CodeGen/TwoAddressInstructionPass.cpp
The file was modifiedllvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
The file was modifiedllvm/include/llvm/CodeGen/VirtRegMap.h
The file was modifiedllvm/lib/CodeGen/RegisterScavenging.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
The file was modifiedllvm/lib/Target/Hexagon/RDFRegisters.h
The file was modifiedllvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
The file was modifiedllvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
The file was modifiedllvm/lib/CodeGen/ExpandPostRAPseudos.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
The file was modifiedllvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
The file was modifiedllvm/lib/Target/Mips/MipsOptimizePICCall.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
The file was modifiedllvm/include/llvm/CodeGen/RegisterPressure.h
The file was modifiedllvm/lib/Target/AMDGPU/R600RegisterInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIFoldOperands.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
The file was modifiedllvm/lib/Target/X86/X86OptimizeLEAs.cpp
The file was modifiedllvm/lib/Target/Hexagon/RDFLiveness.cpp
The file was modifiedllvm/lib/CodeGen/MachineBasicBlock.cpp
The file was modifiedllvm/lib/CodeGen/MIRParser/MIParser.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
The file was modifiedllvm/lib/CodeGen/LiveDebugValues.cpp
The file was modifiedllvm/lib/CodeGen/RegAllocBase.cpp
The file was modifiedllvm/lib/CodeGen/MachineCSE.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonGenInsert.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetRegisterInfo.h
The file was modifiedllvm/lib/CodeGen/StackSlotColoring.cpp
The file was modifiedllvm/include/llvm/CodeGen/RegisterClassInfo.h
The file was modifiedllvm/lib/CodeGen/MachineTraceMetrics.cpp
The file was modifiedllvm/lib/CodeGen/LivePhysRegs.cpp
The file was modifiedllvm/lib/CodeGen/MIRParser/MIRParser.cpp
The file was modifiedllvm/lib/CodeGen/MachineLICM.cpp
The file was modifiedllvm/lib/Target/AMDGPU/GCNRegPressure.h
The file was modifiedllvm/include/llvm/CodeGen/LiveRegUnits.h
The file was modifiedllvm/lib/CodeGen/LiveVariables.cpp
The file was modifiedllvm/lib/CodeGen/MachineInstrBundle.cpp
The file was modifiedllvm/lib/CodeGen/MachinePipeliner.cpp
The file was modifiedllvm/lib/CodeGen/RegAllocGreedy.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonPeephole.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp
The file was modifiedllvm/lib/Target/ARM/ARMScheduleA9.td
The file was modifiedllvm/lib/CodeGen/RegAllocPBQP.cpp
The file was modifiedllvm/lib/CodeGen/LiveStacks.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
The file was modifiedllvm/lib/Target/BPF/BPFMIPeephole.cpp
The file was modifiedllvm/lib/CodeGen/StackMaps.cpp
The file was modifiedllvm/lib/Target/Hexagon/RDFRegisters.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64CondBrTuning.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
The file was modifiedllvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyPrepareForLiveIntervals.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonBitTracker.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
The file was modifiedllvm/lib/CodeGen/MachineVerifier.cpp
The file was modifiedllvm/lib/CodeGen/LiveRangeCalc.cpp
The file was modifiedllvm/lib/CodeGen/RenameIndependentSubregs.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/ARM/ThumbRegisterInfo.cpp
The file was modifiedllvm/lib/CodeGen/LiveRegUnits.cpp
The file was modifiedllvm/lib/CodeGen/OptimizePHIs.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.h
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
The file was modifiedllvm/lib/Target/ARM/A15SDOptimizer.cpp
The file was modifiedllvm/lib/CodeGen/MIRCanonicalizerPass.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/Utils.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
The file was modifiedllvm/lib/CodeGen/ProcessImplicitDefs.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
The file was modifiedllvm/lib/CodeGen/BranchFolding.cpp
The file was modifiedllvm/lib/Target/AMDGPU/R600MachineScheduler.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
The file was modifiedllvm/lib/Target/Hexagon/RDFCopy.cpp
The file was modifiedllvm/lib/Target/X86/X86FlagsCopyLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86InstructionSelector.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
The file was modifiedllvm/lib/CodeGen/RegisterPressure.cpp
The file was modifiedllvm/lib/CodeGen/TargetRegisterInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
The file was modifiedllvm/lib/CodeGen/LiveRangeEdit.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp
The file was modifiedllvm/lib/Target/ARM/ARMCallLowering.cpp
The file was modifiedllvm/lib/CodeGen/ScheduleDAGInstrs.cpp
The file was modifiedllvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
The file was modifiedllvm/lib/Target/Lanai/LanaiInstrInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCVSXCopy.cpp
The file was modifiedllvm/lib/Target/ARM/ARMInstructionSelector.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/lib/CodeGen/LiveIntervals.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/CodeGen/CalcSpillWeights.cpp
The file was modifiedllvm/lib/CodeGen/LiveRangeShrink.cpp
The file was modifiedllvm/lib/CodeGen/LiveInterval.cpp
The file was modifiedllvm/lib/Target/AMDGPU/R600ISelLowering.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyRegNumbering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
The file was modifiedllvm/lib/CodeGen/PHIElimination.cpp
The file was modifiedllvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/FastISel.cpp
The file was modifiedllvm/lib/Target/ARM/ARMAsmPrinter.cpp
The file was modifiedllvm/lib/CodeGen/DeadMachineInstructionElim.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
The file was modifiedllvm/lib/Target/ARM/Thumb1InstrInfo.cpp
The file was modifiedllvm/lib/CodeGen/RegisterCoalescer.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
The file was modifiedllvm/lib/Target/Hexagon/RDFGraph.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIFixupVectorISel.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
The file was modifiedllvm/lib/Target/ARM/MLxExpansionPass.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
The file was modifiedllvm/lib/CodeGen/LiveDebugVariables.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
The file was modifiedllvm/lib/CodeGen/PeepholeOptimizer.cpp
The file was modifiedllvm/lib/Target/Hexagon/BitTracker.cpp
The file was modifiedllvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
The file was modifiedllvm/lib/Target/X86/X86DomainReassignment.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/R600InstrInfo.cpp
The file was modifiedllvm/lib/CodeGen/MachineCombiner.cpp
The file was modifiedllvm/include/llvm/CodeGen/MachineRegisterInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/Mips/MipsInstructionSelector.cpp
The file was modifiedllvm/lib/Target/X86/X86CmovConversion.cpp
The file was modifiedllvm/lib/CodeGen/VirtRegMap.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
The file was modifiedllvm/lib/CodeGen/TailDuplicator.cpp
The file was modifiedllvm/lib/Target/X86/X86CallFrameOptimization.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonSubtarget.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
The file was modifiedllvm/lib/CodeGen/TargetInstrInfo.cpp
The file was modifiedllvm/lib/CodeGen/MachineCopyPropagation.cpp
The file was modifiedllvm/lib/Target/NVPTX/NVPTXPeephole.cpp
The file was modifiedllvm/lib/CodeGen/EarlyIfConversion.cpp
The file was modifiedllvm/lib/Target/Mips/Mips16InstrInfo.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyUtilities.cpp
The file was modifiedllvm/lib/CodeGen/MachineScheduler.cpp
The file was modifiedllvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
The file was modifiedllvm/lib/CodeGen/InlineSpiller.cpp
The file was modifiedllvm/lib/CodeGen/MIRPrinter.cpp
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCMIPeephole.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
The file was modifiedllvm/lib/CodeGen/MachineRegisterInfo.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
The file was modifiedllvm/lib/CodeGen/DetectDeadLanes.cpp
The file was modifiedllvm/lib/CodeGen/MachineInstr.cpp
The file was modifiedllvm/include/llvm/CodeGen/MachineInstrBuilder.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
The file was modifiedllvm/lib/Target/ARM/Thumb2InstrInfo.cpp
Commit 2264f96c2a3b5db3df1a33b15cc32f1797d47d2d by listmail
[Tests] Autogen a bunch of Reassociate tests for ease of update
llvm-svn: 367634
The file was modifiedllvm/test/Transforms/Reassociate/canonicalize-neg-const.ll
The file was modifiedllvm/test/Transforms/Reassociate/mixed-fast-nonfast-fp.ll
The file was modifiedllvm/test/Transforms/Reassociate/xor_reassoc.ll
The file was modifiedllvm/test/Transforms/Reassociate/2002-05-15-SubReassociate.ll
The file was modifiedllvm/test/Transforms/Reassociate/fast-multistep.ll
The file was modifiedllvm/test/Transforms/Reassociate/no-op.ll
The file was modifiedllvm/test/Transforms/Reassociate/commute.ll
The file was modifiedllvm/test/Transforms/Reassociate/propagate-flags.ll
The file was modifiedllvm/test/Transforms/Reassociate/fast-SubReassociate.ll
The file was modifiedllvm/test/Transforms/Reassociate/mulfactor.ll
The file was modifiedllvm/test/Transforms/Reassociate/optional-flags.ll
The file was modifiedllvm/test/Transforms/Reassociate/shift-factor.ll
The file was modifiedllvm/test/Transforms/Reassociate/wrap-flags.ll
The file was modifiedllvm/test/Transforms/Reassociate/looptest.ll
The file was modifiedllvm/test/Transforms/Reassociate/2002-05-15-MissedTree.ll
The file was modifiedllvm/test/Transforms/Reassociate/multistep.ll
The file was modifiedllvm/test/Transforms/Reassociate/fast-fp-commute.ll
The file was modifiedllvm/test/Transforms/Reassociate/vaarg_movable.ll
Commit f93d162e335320c5c33f7ae9f6cc94cce2494f6d by Jonas Devlieghere
[dsymutil] Fix heap-use-after-free related to the LinkOptions.
In r367348, I changed dsymutil to pass the LinkOptions by value isntead
of by const reference. However, the options were still captured by
reference in the LinkLambda. This patch fixes that by passing them in by
value.
llvm-svn: 367635
The file was modifiedllvm/tools/dsymutil/dsymutil.cpp
Commit 1055a11d1bc70f80e78adba816626668941136a4 by daniel_l_sanders
Prevent vregs leaking into the MC layer via
TargetRegisterClass::contains()
Summary: The MC layer doesn't expect to deal with vregs but
TargetRegisterClass::contains() forwards into
MCRegisterClass::contains() and this can cause vregs to turn up in the
MC layer APIs. Add guards against this to prevent this becoming a
problem as we replace unsigned with a new MCRegister object for improved
type safety.
Reviewers: arsenm
Subscribers: wdng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65554
llvm-svn: 367636
The file was modifiedllvm/include/llvm/CodeGen/TargetRegisterInfo.h
Commit 12961ff0fad91d9e51329a1e59213499e33eb3a0 by daniel_l_sanders
Fix up an unused variable warning caused by TRI->isVirtualRegister() ->
Register::isVirtualRegister()
llvm-svn: 367637
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
Commit e063eccc19c51572db67cf0689b594b3e5dc4d9e by Jonas Devlieghere
Format OptionEnumValueElement (NFC)
Reformat OptionEnumValueElement to make it easier to distinguish between
its fields. This also removes the need to disable clang-format for these
arrays.
Differential revision: https://reviews.llvm.org/D65489
llvm-svn: 367638
The file was modifiedlldb/source/Interpreter/OptionGroupWatchpoint.cpp
The file was modifiedlldb/source/Plugins/DynamicLoader/Darwin-Kernel/DynamicLoaderDarwinKernel.cpp
The file was modifiedlldb/source/Commands/CommandObjectExpression.cpp
The file was modifiedlldb/source/Core/Debugger.cpp
The file was modifiedlldb/source/Target/TargetProperties.td
The file was modifiedlldb/source/Commands/CommandObjectWatchpointCommand.cpp
The file was modifiedlldb/source/Commands/CommandObjectBreakpointCommand.cpp
The file was modifiedlldb/source/Target/Target.cpp
The file was modifiedlldb/source/Commands/CommandObjectCommands.cpp
The file was modifiedlldb/source/Commands/CommandObjectTarget.cpp
The file was modifiedlldb/source/Plugins/JITLoader/GDB/JITLoaderGDB.cpp
Commit 975c51c3ff0f83dffb8b01ab06f376924bab7200 by JF Bastien
Update Compiler.h check for MSVC We require at least MSVC 2017, but I
forgot to update Compiler.h when I updated the MSVC requirement.
llvm-svn: 367639
The file was modifiedllvm/include/llvm/Support/Compiler.h