SuccessChanges

Summary

  1. AMDGPU/GlobalISel: RegBankSelect for G_ZEXTLOAD/G_SEXTLOAD
  2. AMDGPU/GlobalISel: Legalize constant 32-bit loads Legalize by casting to a 64-bit constant address. This isn't how the DAG implements it, but it should.
  3. [RISCV] Support llvm-objdump -M no-aliases and -M numeric Summary: Now that llvm-objdump allows target-specific options, we match the `no-aliases` and `numeric` options for RISC-V, as supported by GNU objdump. This is done by overriding the variables used for the command-line options, so that the command-line options are still supported. This patch updates all tests using `llvm-objdump -riscv-no-aliases` to use `llvm-objdump -M no-aliases`. Reviewers: luismarques, asb Reviewed By: luismarques, asb Subscribers: pzheng, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66139
  4. AMDGPU/GlobalISel: First pass at attempting to legalize load/stores There's still a lot more to do, but this handles decomposing due to alignment. I've gotten it to the point where nothing crashes or infinite loops the legalizer.
  5. [RISCV] Add Option for Printing Architectural Register Names Summary: This is an option primarily to use during testing. Instead of always printing registers using their ABI names, this allows a user to request they are printed with their architectural name. This is then used in the register constraint tests to ensure the mapping between architectural and abi names is correct. Reviewers: asb, luismarques Reviewed By: asb Subscribers: pzheng, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65950
  6. Don't emit .gnu_pubnames when tuning for LLDB. LLDB reads the various .apple* accelerator tables (and in the near future: the DWARF 5 accelerator tables) which should make .gnu_pubnames redundant. This changes the Clang driver to no longer pass -ggnu-pubnames when tuning for LLDB. Thanks to David Blaikie for pointing this out! http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20190422/thread.html#646062 rdar://problem/50142073 Differential Revision: https://reviews.llvm.org/D67373
  7. [x86] add a test for BreakFalseDeps; NFC As discussed in D67363
Revision 371536 by arsenm:
AMDGPU/GlobalISel: RegBankSelect for G_ZEXTLOAD/G_SEXTLOAD
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (diff)llvm.src/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (diff)llvm.src/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
Revision 371535 by arsenm:
AMDGPU/GlobalISel: Legalize constant 32-bit loads

Legalize by casting to a 64-bit constant address. This isn't how the
DAG implements it, but it should.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h (diff)llvm.src/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (diff)llvm.src/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.h (diff)llvm.src/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir
Revision 371534 by lenary:
[RISCV] Support llvm-objdump -M no-aliases and -M numeric

Summary:
Now that llvm-objdump allows target-specific options, we match the
`no-aliases` and `numeric` options for RISC-V, as supported by GNU objdump.

This is done by overriding the variables used for the command-line options, so
that the command-line options are still supported.

This patch updates all tests using `llvm-objdump -riscv-no-aliases` to use
`llvm-objdump -M no-aliases`.

Reviewers: luismarques, asb

Reviewed By: luismarques, asb

Subscribers: pzheng, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66139
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp (diff)llvm.src/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
The file was modified/llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h (diff)llvm.src/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
The file was modified/llvm/trunk/test/CodeGen/RISCV/compress-inline-asm.ll (diff)llvm.src/test/CodeGen/RISCV/compress-inline-asm.ll
The file was modified/llvm/trunk/test/CodeGen/RISCV/compress.ll (diff)llvm.src/test/CodeGen/RISCV/compress.ll
The file was modified/llvm/trunk/test/CodeGen/RISCV/option-norvc.ll (diff)llvm.src/test/CodeGen/RISCV/option-norvc.ll
The file was modified/llvm/trunk/test/CodeGen/RISCV/option-rvc.ll (diff)llvm.src/test/CodeGen/RISCV/option-rvc.ll
The file was modified/llvm/trunk/test/MC/RISCV/align.s (diff)llvm.src/test/MC/RISCV/align.s
The file was modified/llvm/trunk/test/MC/RISCV/cnop.s (diff)llvm.src/test/MC/RISCV/cnop.s
The file was modified/llvm/trunk/test/MC/RISCV/compress-cjal.s (diff)llvm.src/test/MC/RISCV/compress-cjal.s
The file was modified/llvm/trunk/test/MC/RISCV/compress-rv32d.s (diff)llvm.src/test/MC/RISCV/compress-rv32d.s
The file was modified/llvm/trunk/test/MC/RISCV/compress-rv32f.s (diff)llvm.src/test/MC/RISCV/compress-rv32f.s
The file was modified/llvm/trunk/test/MC/RISCV/compress-rv32i.s (diff)llvm.src/test/MC/RISCV/compress-rv32i.s
The file was modified/llvm/trunk/test/MC/RISCV/compress-rv64i.s (diff)llvm.src/test/MC/RISCV/compress-rv64i.s
The file was modified/llvm/trunk/test/MC/RISCV/csr-aliases.s (diff)llvm.src/test/MC/RISCV/csr-aliases.s
The file was modified/llvm/trunk/test/MC/RISCV/fixups-compressed.s (diff)llvm.src/test/MC/RISCV/fixups-compressed.s
The file was modified/llvm/trunk/test/MC/RISCV/fixups.s (diff)llvm.src/test/MC/RISCV/fixups.s
The file was modified/llvm/trunk/test/MC/RISCV/numeric-reg-names-d.s (diff)llvm.src/test/MC/RISCV/numeric-reg-names-d.s
The file was modified/llvm/trunk/test/MC/RISCV/numeric-reg-names-f.s (diff)llvm.src/test/MC/RISCV/numeric-reg-names-f.s
The file was modified/llvm/trunk/test/MC/RISCV/numeric-reg-names.s (diff)llvm.src/test/MC/RISCV/numeric-reg-names.s
The file was modified/llvm/trunk/test/MC/RISCV/option-mix.s (diff)llvm.src/test/MC/RISCV/option-mix.s
The file was modified/llvm/trunk/test/MC/RISCV/option-rvc.s (diff)llvm.src/test/MC/RISCV/option-rvc.s
The file was modified/llvm/trunk/test/MC/RISCV/priv-valid.s (diff)llvm.src/test/MC/RISCV/priv-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv32-relaxation.s (diff)llvm.src/test/MC/RISCV/rv32-relaxation.s
The file was modified/llvm/trunk/test/MC/RISCV/rv32a-valid.s (diff)llvm.src/test/MC/RISCV/rv32a-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv32c-aliases-valid.s (diff)llvm.src/test/MC/RISCV/rv32c-aliases-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv32c-only-valid.s (diff)llvm.src/test/MC/RISCV/rv32c-only-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv32c-valid.s (diff)llvm.src/test/MC/RISCV/rv32c-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv32d-valid.s (diff)llvm.src/test/MC/RISCV/rv32d-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv32dc-valid.s (diff)llvm.src/test/MC/RISCV/rv32dc-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv32e-invalid.s (diff)llvm.src/test/MC/RISCV/rv32e-invalid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv32e-valid.s (diff)llvm.src/test/MC/RISCV/rv32e-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv32f-valid.s (diff)llvm.src/test/MC/RISCV/rv32f-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv32fc-aliases-valid.s (diff)llvm.src/test/MC/RISCV/rv32fc-aliases-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv32fc-valid.s (diff)llvm.src/test/MC/RISCV/rv32fc-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv32i-aliases-valid.s (diff)llvm.src/test/MC/RISCV/rv32i-aliases-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv32i-valid.s (diff)llvm.src/test/MC/RISCV/rv32i-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv32m-valid.s (diff)llvm.src/test/MC/RISCV/rv32m-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv64-relaxation.s (diff)llvm.src/test/MC/RISCV/rv64-relaxation.s
The file was modified/llvm/trunk/test/MC/RISCV/rv64a-aliases-valid.s (diff)llvm.src/test/MC/RISCV/rv64a-aliases-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv64a-valid.s (diff)llvm.src/test/MC/RISCV/rv64a-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv64c-aliases-valid.s (diff)llvm.src/test/MC/RISCV/rv64c-aliases-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv64c-hints-valid.s (diff)llvm.src/test/MC/RISCV/rv64c-hints-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv64c-valid.s (diff)llvm.src/test/MC/RISCV/rv64c-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv64d-aliases-valid.s (diff)llvm.src/test/MC/RISCV/rv64d-aliases-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv64d-valid.s (diff)llvm.src/test/MC/RISCV/rv64d-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv64dc-valid.s (diff)llvm.src/test/MC/RISCV/rv64dc-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv64f-aliases-valid.s (diff)llvm.src/test/MC/RISCV/rv64f-aliases-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv64f-valid.s (diff)llvm.src/test/MC/RISCV/rv64f-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv64i-aliases-valid.s (diff)llvm.src/test/MC/RISCV/rv64i-aliases-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv64i-valid.s (diff)llvm.src/test/MC/RISCV/rv64i-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rv64m-valid.s (diff)llvm.src/test/MC/RISCV/rv64m-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rva-aliases-valid.s (diff)llvm.src/test/MC/RISCV/rva-aliases-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rvc-aliases-valid.s (diff)llvm.src/test/MC/RISCV/rvc-aliases-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rvc-hints-valid.s (diff)llvm.src/test/MC/RISCV/rvc-hints-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rvd-aliases-valid.s (diff)llvm.src/test/MC/RISCV/rvd-aliases-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rvdc-aliases-valid.s (diff)llvm.src/test/MC/RISCV/rvdc-aliases-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rvf-aliases-valid.s (diff)llvm.src/test/MC/RISCV/rvf-aliases-valid.s
The file was modified/llvm/trunk/test/MC/RISCV/rvi-aliases-valid.s (diff)llvm.src/test/MC/RISCV/rvi-aliases-valid.s
Revision 371533 by arsenm:
AMDGPU/GlobalISel: First pass at attempting to legalize load/stores

There's still a lot more to do, but this handles decomposing due to
alignment. I've gotten it to the point where nothing crashes or
infinite loops the legalizer.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (diff)llvm.src/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (diff)llvm.src/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h (diff)llvm.src/lib/Target/AMDGPU/SIISelLowering.h
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
The file was removed/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-load.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/legalize-load.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
Revision 371531 by lenary:
[RISCV] Add Option for Printing Architectural Register Names

Summary:
This is an option primarily to use during testing. Instead of always
printing registers using their ABI names, this allows a user to request they
are printed with their architectural name.

This is then used in the register constraint tests to ensure the mapping
between architectural and abi names is correct.

Reviewers: asb, luismarques

Reviewed By: asb

Subscribers: pzheng, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65950
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp (diff)llvm.src/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
The file was modified/llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h (diff)llvm.src/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
The file was added/llvm/trunk/test/MC/RISCV/numeric-reg-names-d.sllvm.src/test/MC/RISCV/numeric-reg-names-d.s
The file was added/llvm/trunk/test/MC/RISCV/numeric-reg-names-f.sllvm.src/test/MC/RISCV/numeric-reg-names-f.s
The file was added/llvm/trunk/test/MC/RISCV/numeric-reg-names.sllvm.src/test/MC/RISCV/numeric-reg-names.s
Revision 371530 by Adrian Prantl:
Don't emit .gnu_pubnames when tuning for LLDB.

LLDB reads the various .apple* accelerator tables (and in the near
future: the DWARF 5 accelerator tables) which should make
.gnu_pubnames redundant. This changes the Clang driver to no longer
pass -ggnu-pubnames when tuning for LLDB.

Thanks to David Blaikie for pointing this out!
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20190422/thread.html#646062

rdar://problem/50142073

Differential Revision: https://reviews.llvm.org/D67373
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/lib/Driver/ToolChains/Clang.cpp (diff)clang.src/lib/Driver/ToolChains/Clang.cpp
The file was modified/cfe/trunk/test/Driver/debug-options.c (diff)clang.src/test/Driver/debug-options.c
Revision 371528 by spatel:
[x86] add a test for BreakFalseDeps; NFC

As discussed in D67363
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/sqrt-partial.ll (diff)llvm.src/test/CodeGen/X86/sqrt-partial.ll