SuccessChanges

Summary

  1. GlobalISel/TableGen: Handle REG_SEQUENCE patterns The scalar f64 patterns don't work yet because they fail on multiple results from the unused implicit def of scc in the result bit operation.
Revision 371542 by arsenm:
GlobalISel/TableGen: Handle REG_SEQUENCE patterns

The scalar f64 patterns don't work yet because they fail on multiple
results from the unused implicit def of scc in the result bit
operation.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (diff)llvm.src/lib/Target/AMDGPU/SIInstructions.td
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
The file was added/llvm/trunk/test/TableGen/GlobalISelEmitterRegSequence.tdllvm.src/test/TableGen/GlobalISelEmitterRegSequence.td
The file was modified/llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp (diff)llvm.src/utils/TableGen/GlobalISelEmitter.cpp