FailedChanges

Summary

  1. [ARM] Fix for buildbots Add --verifymachineinstrs and update the remaining low overhead loop tests.
  2. [RISCV][NFC] Use NoRegister instead of 0 literal Summary: Trivial cleanup. Reviewers: asb, lenary Reviewed By: lenary Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67526
  3. [OpenCL] Tidy up some comments; NFC
  4. [X86] X86DAGToDAGISel::tryFoldLoad - assert root/parent pointers are non-null. NFCI. Silences a static analyzer warning.
  5. InterleavedAccessInfo - Don't dereference a dyn_cast result. NFCI.
  6. [LoopVectorize] Don't dereference a dyn_cast result. NFCI. The static analyzer is warning about potential null dereferences of dyn_cast<> results, we can use cast<> directly as we know that these cases should all be CastInst, which is why its working atm and anyway cast<> will assert if they aren't.
  7. [ARM] Fix for MVE load/store stack accesses MVE loads and stores have a 7 bit immediate range, scaled by the length of the type. This needs to be taught to the stack estimation code to ensure that an emergency spill slot is reserved in case we run out of registers when materialising stack indices. Also the narrowing loads/stores can be created with frame indices even though they do not accept SP as a register. We need in those cases to make sure we have an emergency register to use as the frame base, as SP can never be used. Differential Revision: https://reviews.llvm.org/D67327
  8. Hide implementation details in namespaces.
  9. [ARM][LowOverheadLoops] Add LR def safety check Converting the *LoopStart pseudo instructions into DLS/WLS results in LR being defined. These instructions were inserted on the assumption that LR would already contain the loop counter because a mov is introduced during ISel as the the consumers in the loop can only use LR. That assumption proved wrong! So perform a safety check, finding an appropriate place to insert the DLS/WLS instructions or revert if this isn't possible. Differential Revision: https://reviews.llvm.org/D67539
Revision 372121 by sam_parker:
[ARM] Fix for buildbots

Add --verifymachineinstrs and update the remaining low overhead loop
tests.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir (diff)llvm.src/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir
The file was modified/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir (diff)llvm.src/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir
The file was modified/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir (diff)llvm.src/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir
The file was modified/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir (diff)llvm.src/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir
Revision 372120 by luismarques:
[RISCV][NFC] Use NoRegister instead of 0 literal

Summary: Trivial cleanup.

Reviewers: asb, lenary

Reviewed By: lenary

Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67526
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (diff)llvm.src/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
Revision 372119 by svenvh:
[OpenCL] Tidy up some comments; NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/lib/Sema/OpenCLBuiltins.td (diff)clang.src/lib/Sema/OpenCLBuiltins.td
Revision 372118 by rksimon:
[X86] X86DAGToDAGISel::tryFoldLoad - assert root/parent pointers are non-null. NFCI.

Silences a static analyzer warning.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (diff)llvm.src/lib/Target/X86/X86ISelDAGToDAG.cpp
Revision 372117 by rksimon:
InterleavedAccessInfo - Don't dereference a dyn_cast result. NFCI.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Analysis/VectorUtils.cpp (diff)llvm.src/lib/Analysis/VectorUtils.cpp
Revision 372116 by rksimon:
[LoopVectorize] Don't dereference a dyn_cast result. NFCI.

The static analyzer is warning about potential null dereferences of dyn_cast<> results, we can use cast<> directly as we know that these cases should all be CastInst, which is why its working atm and anyway cast<> will assert if they aren't.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/Vectorize/LoopVectorize.cpp (diff)llvm.src/lib/Transforms/Vectorize/LoopVectorize.cpp
Revision 372114 by dmgreen:
[ARM] Fix for MVE load/store stack accesses

MVE loads and stores have a 7 bit immediate range, scaled by the length of the type. This needs to be taught to the stack estimation code to ensure that an emergency spill slot is reserved in case we run out of registers when materialising stack indices.

Also the narrowing loads/stores can be created with frame indices even though they do not accept SP as a register. We need in those cases to make sure we have an emergency register to use as the frame base, as SP can never be used.

Differential Revision: https://reviews.llvm.org/D67327
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (diff)llvm.src/lib/Target/ARM/ARMFrameLowering.cpp
The file was added/llvm/trunk/test/CodeGen/Thumb2/mve-stacksplot.mirllvm.src/test/CodeGen/Thumb2/mve-stacksplot.mir
Revision 372113 by d0k:
Hide implementation details in namespaces.
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/lib/Sema/SemaLookup.cpp (diff)clang.src/lib/Sema/SemaLookup.cpp
The file was modified/llvm/trunk/lib/CodeGen/MIRVRegNamerUtils.h (diff)llvm.src/lib/CodeGen/MIRVRegNamerUtils.h
The file was modified/llvm/trunk/lib/CodeGen/ModuloSchedule.cpp (diff)llvm.src/lib/CodeGen/ModuloSchedule.cpp
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (diff)llvm.src/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/ARM/MVEVPTBlockPass.cpp (diff)llvm.src/lib/Target/ARM/MVEVPTBlockPass.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (diff)llvm.src/lib/Target/X86/X86FrameLowering.cpp
The file was modified/llvm/trunk/lib/Transforms/IPO/Attributor.cpp (diff)llvm.src/lib/Transforms/IPO/Attributor.cpp
Revision 372111 by sam_parker:
[ARM][LowOverheadLoops] Add LR def safety check

Converting the *LoopStart pseudo instructions into DLS/WLS results in
LR being defined. These instructions were inserted on the assumption
that LR would already contain the loop counter because a mov is
introduced during ISel as the the consumers in the loop can only use
LR. That assumption proved wrong!

So perform a safety check, finding an appropriate place to insert the
DLS/WLS instructions or revert if this isn't possible.

Differential Revision: https://reviews.llvm.org/D67539
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/ARM/ARMLowOverheadLoops.cpp (diff)llvm.src/lib/Target/ARM/ARMLowOverheadLoops.cpp
The file was modified/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir (diff)llvm.src/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir
The file was modified/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir (diff)llvm.src/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
The file was added/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mirllvm.src/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir
The file was modified/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir (diff)llvm.src/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir
The file was modified/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-read.mir (diff)llvm.src/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-read.mir
The file was removed/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-spill.mirllvm.src/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-spill.mir
The file was modified/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-write.mir (diff)llvm.src/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-write.mir
The file was modified/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir (diff)llvm.src/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir
The file was modified/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir (diff)llvm.src/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir
The file was added/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mirllvm.src/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir
The file was added/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-liveout.mirllvm.src/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-liveout.mir
The file was added/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mirllvm.src/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir
The file was modified/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir (diff)llvm.src/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir
The file was modified/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/while.mir (diff)llvm.src/test/CodeGen/Thumb2/LowOverheadLoops/while.mir