SuccessChanges

Summary

  1. [X86][TableGen] Allow timm to appear in output patterns. Use it to remove ConvertToTarget opcodes from the X86 isel table. We're now using a lot more TargetConstant nodes in SelectionDAG. But we were still telling isel to convert some of them to TargetConstants even though they already are. This is because isel emits a conversion anytime the output pattern has a an 'imm'. I guess for patterns in instructions we take the 'timm' from the 'set' pattern, but for Pat patterns with explcicit output we previously had to say 'imm' since 'timm' wasn't allowed in outputs.
  2. [NFC][X86] Add BEXTR test with load and 33-bit mask (PR43381 / D67875)
Revision 372525 by ctopper:
[X86][TableGen] Allow timm to appear in output patterns. Use it to remove ConvertToTarget opcodes from the X86 isel table.

We're now using a lot more TargetConstant nodes in SelectionDAG.
But we were still telling isel to convert some of them
to TargetConstants even though they already are. This is because
isel emits a conversion anytime the output pattern has a an 'imm'.
I guess for patterns in instructions we take the 'timm' from the
'set' pattern, but for Pat patterns with explcicit output we
previously had to say 'imm' since 'timm' wasn't allowed in outputs.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86InstrAVX512.td (diff)llvm.src/lib/Target/X86/X86InstrAVX512.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrSSE.td (diff)llvm.src/lib/Target/X86/X86InstrSSE.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrXOP.td (diff)llvm.src/lib/Target/X86/X86InstrXOP.td
The file was modified/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (diff)llvm.src/utils/TableGen/CodeGenDAGPatterns.cpp
Revision 372524 by lebedevri:
[NFC][X86] Add BEXTR test with load and 33-bit mask (PR43381 / D67875)
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/bmi-x86_64.ll (diff)llvm.src/test/CodeGen/X86/bmi-x86_64.ll