1. DWARFExpression: Fix/add support for (v4) debug_loc base address (details)
  2. [DebugInfo] Fix truncation of call site immediates (details)
  3. [llvm-size] Tidy up error messages (PR42970) (details)
  4. [AArch64] Stackframe accesses to SVE objects. (details)
  5. [Alignment][NFC] Move and type functions from MathExtras to Alignment (details)
  6. [RISCV] enable LTO support, pass some options to linker. (details)
  7. [CostModel][X86] Add CTPOP scalar costs (PR43656) (details)
  8. minidump: Use yaml for memory info tests (details)
  9. [ARM] Add some VMOVN tests. NFC (details)
  10. [libc++][test] Silence more warnings in variant tests (details)
  11. [x86] add tests for possible select to sra transforms; NFC (details)
  12. Revert r374771 "[llvm-size] Tidy up error messages (PR42970)" (details)
  13. [ARM] Selection for MVE VMOVN (details)
  14. [IRBuilder] Update IRBuilder::CreateFNeg(...) to return a UnaryOperator (details)
  15. [x86] adjust select to sra tests; NFC (details)
Commit 5a8db8496440b9d6ced91bd24f4b6b463acc7d55 by pavel
DWARFExpression: Fix/add support for (v4) debug_loc base address
selection entries
The DWARFExpression is parsing the location lists in about five places.
Of those, only one actually had proper support for base address
selection entries.
Since r374600, llvm has started to produce location expressions with
base address selection entries more aggresively, which caused some tests
to fail.
This patch adds support for these entries to the places which had it
missing, fixing the failing tests. It also adds a targeted test for the
two of the three fixes, which should continue testing this functionality
even if the llvm output changes. I am not aware of a way to write a
targeted test for the third fix (DWARFExpression::Evaluate).
llvm-svn: 374769
The file was modifiedlldb/source/Expression/DWARFExpression.cpp
The file was modifiedlldb/test/Shell/SymbolFile/DWARF/debug_loc.s
Commit 8535bed79504ffe3ed7f2de8c158a17e79e54736 by david.stenberg
[DebugInfo] Fix truncation of call site immediates
Summary: This addresses a bug in collectCallSiteParameters() where call
site immediates would be truncated from int64_t to unsigned.
This fixes PR43525.
Reviewers: djtodoro, NikolaPrica, aprantl, vsk
Reviewed By: aprantl
Subscribers: hiraditya, llvm-commits
Tags: #debug-info, #llvm
Differential Revision:
llvm-svn: 374770
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
The file was addedllvm/test/DebugInfo/X86/dbgcall-site-64-bit-imms.ll
Commit 83e52f5e1150018329b8907bb014c77ac382d611 by maskray
[llvm-size] Tidy up error messages (PR42970)
Clean up some formatting inconsistencies in the error messages and
correctly exit with non-zero in all error cases.
Differential Revision: Patch by Alex
llvm-svn: 374771
The file was modifiedllvm/test/tools/llvm-size/invalid-input.test
The file was modifiedllvm/tools/llvm-size/llvm-size.cpp
The file was modifiedllvm/test/tools/llvm-size/no-input.test
Commit 77748129650271ebd7b3f9c2c6c4f8110cb4a845 by sander.desmalen
[AArch64] Stackframe accesses to SVE objects.
Materialize accesses to SVE frame objects from SP or FP, whichever is
available and beneficial.
This patch still assumes the objects are pre-allocated. The automatic
layout of SVE objects within the stackframe will be added in a separate
Reviewers: greened, cameron.mcinally, efriedma, rengolin, thegameg,
Reviewed By: cameron.mcinally
Differential Revision:
llvm-svn: 374772
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
The file was modifiedllvm/test/CodeGen/AArch64/framelayout-sve.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.h
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.cpp
Commit ce56e1a1cc5714f4af5675dd963cfebed766d9e1 by gchatelet
[Alignment][NFC] Move and type functions from MathExtras to Alignment
Summary: This is patch is part of a series to introduce an Alignment
type. See this thread for context: See this
patch for the introduction of the type:
Reviewers: courbet
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision:
llvm-svn: 374773
The file was modifiedllvm/unittests/Support/TrailingObjectsTest.cpp
The file was modifiedllvm/include/llvm/Support/BinaryStreamArray.h
The file was modifiedllvm/include/llvm/Support/BinaryStreamReader.h
The file was modifiedllvm/include/llvm/Support/MathExtras.h
The file was modifiedllvm/lib/ProfileData/Coverage/CoverageMappingReader.cpp
The file was modifiedllvm/lib/Support/Unix/
The file was modifiedllvm/include/llvm/Support/Allocator.h
The file was modifiedllvm/unittests/Support/AlignmentTest.cpp
The file was modifiedllvm/unittests/Support/AllocatorTest.cpp
The file was modifiedllvm/include/llvm/Support/Alignment.h
The file was modifiedllvm/include/llvm/Support/TrailingObjects.h
Commit cdcf58e5af025989a8dd52bc0d9c032712a160c8 by selliott
[RISCV] enable LTO support, pass some options to linker.
Summary: 1. enable LTO need to pass target feature and abi to LTO code
  RISCV backend need the target feature to decide which extension used
  code generation. 2. move getTargetFeatures to CommonArgs.h and add
ForLTOPlugin flag 3. add general tools::getTargetABI in CommonArgs.h
because different target uses different
  way to get the target ABI.
Patch by Kuan Hsu Chen (khchen)
Reviewers: lenary, lewis-revill, asb, MaskRay
Reviewed By: lenary
Subscribers: hiraditya, dschuff, aheejin, fedor.sergeev, mehdi_amini,
inglorion, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD,
kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, steven_wu,
rogfer01, MartinMosbeck, brucehoult, the_o, dexonsmith, rkruppe, PkmX,
jocewei, psnobl, benna, Jim, lenary, s.egerton, pzheng, cfe-commits
Tags: #clang
Differential Revision:
llvm-svn: 374774
The file was modifiedclang/lib/Driver/ToolChains/RISCVToolchain.cpp
The file was modifiedclang/lib/Driver/ToolChains/RISCVToolchain.h
The file was modifiedclang/lib/Driver/ToolChains/CommonArgs.cpp
The file was modifiedclang/test/Driver/gold-lto.c
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/lib/Driver/ToolChains/CommonArgs.h
Commit 151bbba758610905d1789760124598048192179d by llvm-dev
[CostModel][X86] Add CTPOP scalar costs (PR43656)
Add specific scalar costs for ctpop instructions, these are based on the
llvm-mca's SLM throughput numbers (the oldest model we have).
For targets supporting POPCNT, we provide overrides that assume 1cy
llvm-svn: 374775
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/X86/ctpop.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/ctpop.ll
Commit 458680ac78fab3e699c2a077afe65af39ef3cf4f by pavel
minidump: Use yaml for memory info tests
Also, delete some minidump binary files that are no longer used in any
llvm-svn: 374776
The file was modifiedlldb/unittests/Process/minidump/CMakeLists.txt
The file was modifiedlldb/unittests/Process/minidump/MinidumpParserTest.cpp
The file was removedlldb/unittests/Process/minidump/Inputs/linux-x86_64_not_crashed.dmp
The file was removedlldb/unittests/Process/minidump/Inputs/dump-content.dmp
Commit a5ef3daf1d776384eff624725dfc1738e02ad018 by
[ARM] Add some VMOVN tests. NFC
llvm-svn: 374777
The file was addedllvm/test/CodeGen/Thumb2/mve-vmovn.ll
Commit a4f07b4d2e8d3523cd6454cf8a9410c0cfca0410 by Casey
[libc++][test] Silence more warnings in variant tests
More cases of signed-to-unsigned conversion warnings that missed the
train for d2623522.
llvm-svn: 374778
The file was modifiedlibcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_args.pass.cpp
The file was modifiedlibcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_args.pass.cpp
The file was modifiedlibcxx/test/std/utilities/variant/variant.variant/variant.assign/move.pass.cpp
The file was modifiedlibcxx/test/std/utilities/variant/variant.variant/variant.assign/copy.pass.cpp
Commit 03462bbe7d549e1cbe0d38fbf0b195bb78456a80 by spatel
[x86] add tests for possible select to sra transforms; NFC
llvm-svn: 374779
The file was addedllvm/test/CodeGen/X86/select-sra.ll
Commit 961c34d5f452b07ccd289fe54a8aff8404c9bc59 by nicolasweber
Revert r374771 "[llvm-size] Tidy up error messages (PR42970)"
This reverts commit 83e52f5e1150018329b8907bb014c77ac382d611.
Makes Object/macho-invalid.test fail everywhere, e.g. here:
llvm-svn: 374780
The file was modifiedllvm/test/tools/llvm-size/invalid-input.test
The file was modifiedllvm/test/tools/llvm-size/no-input.test
The file was modifiedllvm/tools/llvm-size/llvm-size.cpp
Commit 543236232c79221c4da261246e49888844697539 by
[ARM] Selection for MVE VMOVN
The adds both VMOVNt and VMOVNb instruction selection from the
appropriate shuffles. We detect shuffle masks of the form: 0, N, 2, N+2,
4, N+4, ... or 0, N+1, 2, N+3, 4, N+5, ... ISel will also try the
opposite patterns, with inputs reversed. These are selected to VMOVNt
and VMOVNb respectively.
Differential Revision:
llvm-svn: 374781
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.h
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/lib/Target/ARM/
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vmovn.ll
Commit 20b8ed2c2b107e037dabe879fb85d3c0734e3004 by cameron.mcinally
[IRBuilder] Update IRBuilder::CreateFNeg(...) to return a UnaryOperator
Reapply r374240 with fix for Ocaml test, namely Bindings/OCaml/
Differential Revision:
llvm-svn: 374782
The file was modifiedllvm/test/Transforms/InstCombine/cos-1.ll
The file was modifiedclang/test/CodeGen/aarch64-neon-intrinsics.c
The file was modifiedclang/test/CodeGen/arm-v8.2a-neon-intrinsics.c
The file was modifiedclang/test/CodeGen/complex-math.c
The file was modifiedclang/test/CodeGen/fma-builtins.c
The file was modifiedllvm/unittests/IR/InstructionsTest.cpp
The file was modifiedllvm/test/Transforms/InstCombine/fast-math.ll
The file was modifiedclang/test/CodeGen/aarch64-neon-2velem.c
The file was modifiedllvm/test/CodeGen/AMDGPU/divrem24-assume.ll
The file was modifiedllvm/test/Transforms/InstCombine/fmul.ll
The file was modifiedclang/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c
The file was modifiedllvm/include/llvm/IR/IRBuilder.h
The file was modifiedllvm/test/Bindings/OCaml/
The file was modifiedclang/test/CodeGen/arm_neon_intrinsics.c
The file was modifiedllvm/test/Transforms/InstCombine/select-crash.ll
The file was modifiedclang/test/CodeGen/aarch64-neon-misc.c
The file was modifiedclang/test/CodeGen/avx512vl-builtins.c
The file was modifiedclang/test/CodeGen/zvector.c
The file was modifiedllvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
The file was modifiedclang/test/CodeGen/fma4-builtins.c
The file was modifiedclang/test/CodeGen/avx512f-builtins.c
The file was modifiedclang/test/CodeGen/fp16-ops.c
The file was modifiedclang/test/CodeGen/aarch64-neon-fma.c
The file was modifiedclang/test/CodeGen/builtins-ppc-vsx.c
The file was modifiedclang/lib/CodeGen/CGExprScalar.cpp
The file was modifiedclang/test/CodeGen/zvector2.c
The file was modifiedclang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c
The file was modifiedclang/test/CodeGen/aarch64-v8.2a-fp16-intrinsics.c
The file was modifiedclang/test/CodeGen/exprs.c
Commit ee86804cf1bc7f9d9935261231b95e8f30dd7c03 by spatel
[x86] adjust select to sra tests; NFC
Avoid demanded-bits-based specializations (that may not be ideal, but
that's another problem).
llvm-svn: 374783
The file was modifiedllvm/test/CodeGen/X86/select-sra.ll