SuccessChanges

Summary

  1. [NFC][ARM][AArch64] More code size tests (details)
  2. [MLIR] Helper class referencing MemRefType to unify runner implementations. (details)
  3. AMDGPU/GlobalISel: Don't select boolean phi by default (details)
  4. [PowerPC] Unaligned FP default should apply to scalars only (details)
  5. Use configure depends to trigger reconfiguration when LLVMBuild files change (details)
  6. GlobalISel: Merge G_PTR_MASK with llvm.ptrmask intrinsic (details)
  7. Debug Info: Mark os_log helper functions as artificial (details)
  8. Add missing forward decl to unbreak the modular build (details)
  9. AMDGPU/GlobalISel: Fix assert on 16-bit G_EXTRACT results (details)
  10. Fix MemoryLocation.h use without Instructions.h (details)
  11. [PowerPC][AIX] Spill CSRs to the ABI specified stack offsets. (details)
  12. [ELF][PPC64] Synthesize _savegpr[01]_{14..31} and _restgpr[01]_{14..31} (details)
  13. [dsymutil] Escape CFBundleIdentifier in plist. (details)
  14. [AMDGPU] NFC target dependent requiresUniformRegister refactored out (details)
  15. Revert "[AMDGPU] NFC target dependent requiresUniformRegister refactored out" (details)
Commit 792575ff323b714d03215951c6fff105f1074aac by sam.parker
[NFC][ARM][AArch64] More code size tests

Add analysis runs for icmp, fcmp and select instructions.
The file was removedllvm/test/Analysis/CostModel/ARM/icmps.ll
The file was addedllvm/test/Analysis/CostModel/AArch64/cmp.ll
The file was modifiedllvm/test/Analysis/CostModel/AArch64/select.ll
The file was modifiedllvm/test/Analysis/CostModel/ARM/select.ll
The file was addedllvm/test/Analysis/CostModel/ARM/cmps.ll
Commit 222e0e58a87649623b3d16ce3fef56a6a0555be3 by csigg
[MLIR] Helper class referencing MemRefType to unify runner implementations.

Summary:
Add DynamicMemRefType which can reference one of the statically ranked StridedMemRefType or a UnrankedMemRefType so that runner utils only need to be implemented once.

There is definitely room for more clean up and unification, but I will keep that for follow-ups.

Reviewers: nicolasvasilache

Reviewed By: nicolasvasilache

Subscribers: mehdi_amini, rriddle, jpienaar, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, liufengdb, stephenneuendorffer, Joonsoo, grosul1, frgossen, Kayjukh, jurahul, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80513
The file was modifiedmlir/tools/mlir-cuda-runner/cuda-runtime-wrappers.cpp
The file was modifiedmlir/test/mlir-cpu-runner/utils.mlir
The file was modifiedmlir/include/mlir/ExecutionEngine/CRunnerUtils.h
The file was modifiedmlir/lib/ExecutionEngine/RunnerUtils.cpp
The file was modifiedmlir/test/mlir-cpu-runner/unranked_memref.mlir
The file was modifiedmlir/include/mlir/ExecutionEngine/RunnerUtils.h
Commit 2dd7714b8d264f6436b56582e4448f6a003a61fc by Matthew.Arsenault
AMDGPU/GlobalISel: Don't select boolean phi by default

This is currently missing most of the hard parts to lower correctly,
so disable it for now. This fixes at least one OpenCL conformance test
and allows it to pass with fallback. Hide this behind an option for
now.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
Commit 099a875f28d0131a6ae85af91b9eb8627917fbbe by nemanja.i.ibm
[PowerPC] Unaligned FP default should apply to scalars only

As reported in PR45186, we could be in a situation where we don't
want to handle unaligned memory accesses for FP scalars but still
have VSX (which allows unaligned access for vectors). Change the
default to only apply to scalars.

Fixes: https://bugs.llvm.org/show_bug.cgi?id=45186
The file was addedllvm/test/CodeGen/PowerPC/pr45186.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
Commit e72cba975735c2202b254621d79fb9dbbed08d39 by David.Chisnall
Use configure depends to trigger reconfiguration when LLVMBuild files change

Summary:
The existing logic has a workaround where configure_file is used to write a single dummy file output many times.

CMake has a feature to more directly add the dependency and avoid the dummy file (it is available in the minimum version specified).

Reviewers: theraven

Reviewed By: theraven

Subscribers: theraven, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80218
The file was modifiedllvm/utils/llvm-build/llvmbuild/main.py
Commit 8bc03d2168241f7b12265e9cd7e4eb7655709f34 by Matthew.Arsenault
GlobalISel: Merge G_PTR_MASK with llvm.ptrmask intrinsic

Confusingly, these were unrelated and had different semantics. The
G_PTR_MASK instruction predates the llvm.ptrmask intrinsic, but has a
different format. G_PTR_MASK only allows clearing the low bits of a
pointer, and only a constant number of bits. The ptrmask intrinsic
allows an arbitrary mask. Replace G_PTR_MASK to match the intrinsic.

Only selects the cases that look like the old instruction. More work
is needed to select the general case. Also new legalization code is
still needed to deal with the case where the incoming mask size does
not match the pointer size, which has a specified behavior in the
langref.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
The file was addedllvm/test/MachineVerifier/test_g_ptrmask.mir
The file was removedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-mask.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select.mir
The file was modifiedllvm/include/llvm/Target/GenericOpcodes.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
The file was modifiedllvm/docs/GlobalISel/GenericOpcode.rst
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll
The file was modifiedllvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
The file was modifiedllvm/lib/CodeGen/MachineVerifier.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
The file was modifiedllvm/include/llvm/Support/TargetOpcodes.def
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrmask.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
Commit b59b3640bcbdfc6cf4b35ff3a6ad5f524a073b45 by Adrian Prantl
Debug Info: Mark os_log helper functions as artificial

The os_log helper functions are linkonce_odr and supposed to be
uniqued across TUs, so attachine a DW_AT_decl_line on it is highly
misleading. By setting the function decl to implicit, CGDebugInfo
properly marks the functions as artificial and uses a default file /
line 0 location for the function.

rdar://problem/63450824

Differential Revision: https://reviews.llvm.org/D80463
The file was addedclang/test/CodeGen/debug-info-oslog.c
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
Commit 6b7d51ad4a16579b0a7d41c77715be4d9e266d8c by Adrian Prantl
Add missing forward decl to unbreak the modular build
The file was modifiedclang/include/clang/Index/IndexingOptions.h
Commit 50d4b22ca0dd8f25a2ab2cb53a04627b2504ecfe by Matthew.Arsenault
AMDGPU/GlobalISel: Fix assert on 16-bit G_EXTRACT results

I consider this to be a hack, since we probably should not mark any
16-bit extract as legal, and require all extracts to be done on
multiples of 32. There are quite a few more battles to fight in the
legalizer for sub-dword vectors, so just select this for now so we can
pass OpenCL conformance without crashing.

Also fix the same assert for G_INSERTs. Unlike G_EXTRACT there's not a
trivial way to select this so just fail on it.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.xfail.mir
Commit 5bd97eb28aff252a3a9e8b0ef00d563b557f5580 by Sanne.Wouda
Fix MemoryLocation.h use without Instructions.h

MemoryLocation.h was changed to only include Instruction.h.  However,
cast<> still needs the full definiton, so move MemoryLocation::getOrNone
to the cpp file.
The file was modifiedllvm/include/llvm/Analysis/MemoryLocation.h
The file was modifiedllvm/lib/Analysis/MemoryLocation.cpp
Commit d6c8736287371f1c9eba3629819209c5fb54e546 by sd.fertile
[PowerPC][AIX] Spill CSRs to the ABI specified stack offsets.

Extend the CSR save/restore insertion code to support both 32-bit and
64-bit AIX.

Differential Revision: https://reviews.llvm.org/D79252
The file was modifiedllvm/lib/Target/PowerPC/PPCFrameLowering.cpp
The file was addedllvm/test/CodeGen/PowerPC/aix-csr.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-cc-abi.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-calleesavedregs.ll
The file was modifiedllvm/test/CodeGen/PowerPC/ppc64-crsave.mir
The file was modifiedllvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix32-crsave.mir
Commit bae7cf674621b5892a036fabe77692a59e2b115b by maskray
[ELF][PPC64] Synthesize _savegpr[01]_{14..31} and _restgpr[01]_{14..31}

In the 64-bit ELF V2 API Specification: Power Architecture, 2.3.3.1. GPR
Save and Restore Functions defines some special functions which may be
referenced by GCC produced assembly (LLVM does not reference them).

With GCC -Os, when the number of call-saved registers exceeds a certain
threshold, GCC generates `_savegpr0_* _restgpr0_*` calls and expects the
linker to define them. See
https://sourceware.org/pipermail/binutils/2002-February/017444.html and
https://sourceware.org/pipermail/binutils/2004-August/036765.html . This
is weird because libgcc.a would be the natural place. However, the linker
generation approach has the advantage that the linker can generate
multiple copies to avoid long branch thunks. We don't consider the
advantage significant enough to complicate our trunk implementation, so
we take a simple approach.

* Check whether `_savegpr0_{14..31}` are used
* If yes, define needed symbols and add an InputSection with the code sequence.

`_savegpr1_*` `_restgpr0_*` and `_restgpr1_*` are similar.

Reviewed By: sfertile

Differential Revision: https://reviews.llvm.org/D79977
The file was modifiedlld/ELF/Writer.cpp
The file was addedlld/test/ELF/ppc64-restgpr0.s
The file was modifiedlld/ELF/Target.h
The file was addedlld/test/ELF/ppc64-restgpr1.s
The file was addedlld/test/ELF/ppc64-savegpr1.s
The file was addedlld/test/ELF/ppc64-savegpr0.s
The file was addedlld/test/ELF/ppc64-saveres.s
The file was modifiedlld/ELF/Arch/PPC64.cpp
Commit d4086213c6d76fcaa5fa620ad680eaaf886cc66e by Jonas Devlieghere
[dsymutil] Escape CFBundleIdentifier in plist.

Revision 333565 started escaping HTML special characters in the plist
written by dsymutil, but didn't include the updated CFBundleIdentifier.
The file was modifiedllvm/test/tools/dsymutil/Inputs/Info.plist
The file was modifiedllvm/test/tools/dsymutil/X86/darwin-bundle.test
The file was modifiedllvm/tools/dsymutil/dsymutil.cpp
Commit fb38b98338cc87442e3451665e82bf1c8ef9388f by alex-t
[AMDGPU] NFC target dependent requiresUniformRegister refactored out

Summary: Target specific method encapsulated into the Target Lowering Info.

Reviewers: rampitec, vpykhtin

Reviewed By: rampitec

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70085
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
Commit 9786e7552d5564268484357866088d0a054bccaf by Matthew.Arsenault
Revert "[AMDGPU] NFC target dependent requiresUniformRegister refactored out"

This reverts commit fb38b98338cc87442e3451665e82bf1c8ef9388f.

This will regress compile time.
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp