SuccessChanges

Summary

  1. [mlir][Vector] Simplify code a bit. NFCI. (details)
  2. [ARM] Distribute post-inc for Thumb2 sign/zero extending loads/stores (details)
  3. [Attributor][NFC] Update description for the dependency graph (details)
  4. [VectorCombine] add tests for non-zero gep offsets; NFC (details)
  5. [LCSSA] Use IRBuilder for PHI creation. (details)
  6. [X86][AVX] Ensure we only combine to PSHUFLW/PSHUFHW on supporting targets (details)
  7. [libcxx] Add compatible with constraint tests for some shared_ptr constructors. (details)
  8. [X86][AVX512] Fold concat(and(x,y),and(z,w)) -> and(concat(x,z),concat(y,w)) for 512-bit vectors (details)
  9. [LCSSA] Provide option for caller to clean up unused PHIs. (details)
  10. [PPC] Adjust run line for hardware-loops-crash.ll (details)
  11. [InstCombine] Fold abs(-x) -> abs(x) (details)
  12. [InstSimplify] Fold abs(abs(x)) -> abs(x) (details)
  13. [X86] Add assembler support for {disp8} and {disp32} to control the size of displacement used for memory operands. (details)
  14. [NewPM][LVI] Abandon LVI after CVP (details)
  15. Updated the -I option description. (details)
  16. [msan] Respect no_huge_pages_for_shadow. (details)
Commit eb41f9edde1070d68fce4a4eb31118e0ec1ca36d by benny.kra
[mlir][Vector] Simplify code a bit. NFCI.
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
The file was modifiedmlir/lib/Dialect/Vector/VectorTransforms.cpp
Commit fd69df62ed1091f25ba4749cc5152e9ce2fe3af4 by david.green
[ARM] Distribute post-inc for Thumb2 sign/zero extending loads/stores

This adds sign/zero extending scalar loads/stores to the MVE
instructions added in D77813, allowing us to create up more post-inc
instructions. These are comparatively simple, compared to LDR/STR (which
may be better turned into an LDRD/LDM), but still require some additions
over MVE instructions. Because there are i12 and i8 variants of the
offset loads/stores dealing with different signs, we may need to convert
an i12 address to a i8 negative instruction. t2LDRBi12 can also be
shrunk to a tLDRi under the right conditions, so we need to be careful
with codesize too.

Differential Revision: https://reviews.llvm.org/D78625
The file was modifiedllvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-float16regloops.ll
The file was modifiedllvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/postinc-distribute.mir
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.h
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
Commit fa30adecc766eb627a85f746b0f6f22b0eadbda8 by clfbbn
[Attributor][NFC] Update description for the dependency graph

The word "dependency graph" is a bit misleading. When there is an
edge from node A to B (A -> B), it actually mean that B depends on
A and when the state of A is updated, B should also be updated. So
I update the comment to make the description clearer.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D85065
The file was modifiedllvm/include/llvm/Transforms/IPO/Attributor.h
Commit d620a6fe98f74d9b305a0d45d4c6804b0e46bf6c by spatel
[VectorCombine] add tests for non-zero gep offsets; NFC
The file was modifiedllvm/test/Transforms/VectorCombine/X86/load.ll
Commit a9b06a2c14f9a38ba16165f0343faaa9ae713fec by flo
[LCSSA] Use IRBuilder for PHI creation.

Use IRBuilder instead PHINode::Create. This should not impact the
generated code, but IRBuilder provides a way to register callbacks for
inserted instructions, which is convenient for some users.

Reviewed By: lebedev.ri

Differential Revision: https://reviews.llvm.org/D85037
The file was modifiedllvm/include/llvm/Transforms/Utils/LoopUtils.h
The file was modifiedllvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
The file was modifiedllvm/lib/Transforms/Utils/LCSSA.cpp
Commit bb13c34c3aa100006461c972319abfef0af70603 by llvm-dev
[X86][AVX] Ensure we only combine to PSHUFLW/PSHUFHW on supporting targets

Noticed while investigating combining from concatenated shuffle vectors, we weren't checking that PSHUFLW/PSHUFHW was legal - we were depending on lowering splitting to subvectors.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 8697d6cfa8947c4033dfe1d2ac708482d75a28d4 by zoecarver
[libcxx] Add compatible with constraint tests for some shared_ptr constructors.

Add shared_ptr tests where the element type and pointer type aren't 'convertible' but are 'compatible'.

Responding to a comment from D81414.

Differential Revision: https://reviews.llvm.org/D81532
The file was modifiedlibcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/pointer_deleter.pass.cpp
The file was modifiedlibcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/pointer_deleter_allocator.pass.cpp
Commit 82a5c848e7f531ee636f643450072059397ac90c by llvm-dev
[X86][AVX512] Fold concat(and(x,y),and(z,w)) -> and(concat(x,z),concat(y,w)) for 512-bit vectors

Helps vpternlog folding on non-AVX512BW targets
The file was modifiedllvm/test/CodeGen/X86/vector-rotate-512.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shift-shl-512.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-rot-512.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-insert-extract.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-512.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shift-lshr-512.ll
The file was modifiedllvm/test/CodeGen/X86/vector-bitreverse.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-512.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-rot-512.ll
The file was modifiedllvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
Commit 05b44f7eaebfbca19999fde149c4c586fc965015 by flo
[LCSSA] Provide option for caller to clean up unused PHIs.

formLCSSAForInstructions is used by SCEVExpander, which tracks all
inserted instructions including LCSSA phis using asserting value
handles. This means cleanup needs to happen in the caller.

Extend formLCSSAForInstructions  to take an optional pointer to a
vector. If this argument is non-nullptr, instead of directly deleting
the phis, add them to the vector, so the caller can process them.

This should address various PPC buildbot failures, including
http://lab.llvm.org:8011/builders/clang-ppc64be-linux-lnt/builds/40567
The file was modifiedllvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
The file was addedllvm/test/CodeGen/PowerPC/hardware-loops-crash.ll
The file was modifiedllvm/include/llvm/Transforms/Utils/LoopUtils.h
The file was modifiedllvm/lib/Transforms/Utils/LCSSA.cpp
Commit 95ddb9ff673001b2745c871c5751d165c2a27546 by flo
[PPC] Adjust run line for hardware-loops-crash.ll

Looks like %s was accidentally dropped.
The file was modifiedllvm/test/CodeGen/PowerPC/hardware-loops-crash.ll
Commit 4a19e6156ed5b6e87d708e6de29b675be69c574f by craig.topper
[InstCombine] Fold abs(-x) -> abs(x)

Negating the input doesn't matter. I left a FIXME to copy the nsw flag if its present on the neg but not on the abs.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D85055
The file was modifiedllvm/test/Transforms/InstCombine/abs-intrinsic.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
Commit 85b5315dbe9d52766ab326e702d638fcf58579b5 by craig.topper
[InstSimplify] Fold abs(abs(x)) -> abs(x)

It's always safe to pick the earlier abs regardless of the nsw flag. We'll just lose it if it is on the outer abs but not the inner abs.

Differential Revision: https://reviews.llvm.org/D85053
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp
The file was modifiedllvm/test/Transforms/InstSimplify/call.ll
Commit e297d928dcde31ac92eff72532095f4f657f2ebd by craig.topper
[X86] Add assembler support for {disp8} and {disp32} to control the size of displacement used for memory operands.

These prefixes should override the default behavior and force a larger immediate size. I don't believe gas issues any warning if you use {disp8} when a 32-bit displacement is already required. And this patch doesn't either.

This completes the {disp8} and {disp32} support from PR46650.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D84793
The file was modifiedllvm/test/MC/X86/x86-64.s
The file was modifiedllvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
Commit 25af353b0e74907d5d50c8616b885bd1f73a68b3 by nikita.ppv
[NewPM][LVI] Abandon LVI after CVP

As mentioned on D70376, LVI can currently cause performance issues
when running under NewPM. The problem is that, unlike the legacy
pass manager, NewPM will not immediately discard the LVI analysis
if the following pass does not need it. This is a problem, because
LVI has a high memory requirement, and mass invalidation of LVI
values is very inefficient. LVI should only be alive during passes
that actively interact with it.

This patch addresses the issue by explicitly abandoning LVI after CVP,
which gets us back to the LegacyPM behavior.

Differential Revision: https://reviews.llvm.org/D84959
The file was modifiedllvm/test/Other/new-pm-defaults.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
The file was modifiedclang/test/CodeGen/thinlto-distributed-newpm.ll
The file was modifiedllvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
The file was modifiedllvm/test/Other/new-pm-thinlto-defaults.ll
Commit 8dd4e3ceb804a58bcf25e6856fc6fde5e1995a66 by alebedev
Updated the -I option description.
The file was modifiedclang/docs/ClangCommandLineReference.rst
The file was modifiedclang/include/clang/Driver/Options.td
Commit dc3388b0209d17f7ee2f4dc3e4f072dc397dd75d by eugenis
[msan] Respect no_huge_pages_for_shadow.

Disable huge pages in the MSan shadow region when
no_huge_pages_for_shadow == true (default).

Differential Revision: https://reviews.llvm.org/D85061
The file was modifiedcompiler-rt/lib/msan/msan_linux.cpp