Started 1 yr 3 mo ago
Took 5 hr 17 min on green-dragon-19

Success Build #18488 (Jul 22, 2019 12:18:45 PM)

  • : 366695
  • : 366694
  • : 366638
  • : 364589
  • : 366606
  • : 366687
  1. TableGen: Support physical register inputs > 255

    This was truncating register value that didn't fit in unsigned char.
    Switch AMDGPU sendmsg intrinsics to using a tablegen pattern. (detail/ViewSVN)
    by arsenm
  2. [NFC] Relaxed regression tests for PR42665

    Following up on the buildbot failures, this commits relaxes some tests:
    instead of checking for specific IR output, it now ensures that the
    underlying issue (the crash), and only that, doesn't happen. (detail/ViewSVN)
    by mantognini
  3. [ARM][LowOverheadLoops] Revert remaining pseudos

    ARMLowOverheadLoops would assert a failure if it did not find all the
    pseudo instructions that comprise the hardware loop. Instead of doing
    this, iterate through all the instructions of the function and revert
    any remaining pseudo instructions that haven't been converted.

    Differential Revision: (detail/ViewSVN)
    by sam_parker
  4. [OPENMP]Add support for analysis of firstprivate variables.

    Firstprivate variables are the variables, for which the private copies
    must be created in the OpenMP regions and must be initialized with the
    original values. Thus, we must report if the uninitialized variable is
    used as firstprivate.

    Reviewers: NoQ

    Subscribers: guansong, jdoerfert, caomhin, kkwli0, cfe-commits

    Tags: #clang

    Differential Revision: (detail/ViewSVN)
    by abataev
  5. AMDGPU/GlobalISel: Fix broken tests (detail/ViewSVN)
    by arsenm
  6. Update documentation for all CERT checks that correspond to a recommendation.

    CERT removed their C++ secure coding recommendations from public view and so the links within that documentation are stale. This updates various pieces of documentation to make this more clear, and to help add substance where our docs deferred to CERT's wiki. (detail/ViewSVN)
    by aaronballman
  7. Reland [ELF] Loose a condition for relocation with a symbol

    This patch was not the reason of the buildbot failure.

    Deleted code was introduced as a work around for a bug in the gold linker
    ( Test case that was given as a reason for
    this part of code, the one on previous link, now works for the gold.
    This condition is too strict and when a code is compiled with debug info
    it forces generation of numerous relocations with symbol for architectures
    that do not have relocation addend.

    Reviewers: arsenm, espindola

    Reviewed By: MaskRay

    Differential Revision: (detail/ViewSVN)
    by nikolaprica
  8. AMDGPU/GlobalISel: Remove unnecessary code

    The minnum/maxnum case are dead, and the cvt is handled by the
    default. (detail/ViewSVN)
    by arsenm
  9. [ARM] Fix for MVE VPT block pass

    We need to ensure that the number of T's is correct when adding multiple
    instructions into the same VPT block.

    Differential revision: (detail/ViewSVN)
    by dmgreen
  10. Updated the signature for some stack related intrinsics (CLANG)

    Modified the intrinsics
    int_frameaddress & int_sponentry.
    This commit depends on the changes in rL366679

    Reviewed By: arsenm

    Differential Revision: (detail/ViewSVN)
    by cdevadas
  11. Revert the change to the [[nodiscard]] feature test macro value.

    This value only gets bumped once both P1301 and P1771 are implemented. (detail/ViewSVN)
    by aaronballman
  12. [X86] EltsFromConsecutiveLoads - support common source loads (REAPPLIED)

    This patch enables us to find the source loads for each element, splitting them into a Load and ByteOffset, and attempts to recognise consecutive loads that are in fact from the same source load.

    A helper function, findEltLoadSrc, recurses to find a LoadSDNode and determines the element's byte offset within it. When attempting to match consecutive loads, byte offsetted loads then attempt to matched against a previous load that has already been confirmed to be a consecutive match.

    Next step towards PR16739 - after this we just need to account for shuffling/repeated elements to create a vector load + shuffle.

    Fixed out of bounds load assert identified in rL366501

    Differential Revision: (detail/ViewSVN)
    by rksimon
  13. AMDGPU/GlobalISel: Fix tests without asserts

    The legality check is only done under NDEBUG, so the failure cases are
    different in a release build. (detail/ViewSVN)
    by arsenm
  14. Added address-space mangling for stack related intrinsics

    Modified the following 3 intrinsics:
    int_frameaddress & int_sponentry.

    Reviewed By: arsenm

    Differential Revision: (detail/ViewSVN)
    by cdevadas
  15. [X86][SSE] Add EltsFromConsecutiveLoads test case identified in rL366501

    Test case that led to rL366441 being reverted at rL366501 (detail/ViewSVN)
    by rksimon
  16. [yaml2obj] - Change how we handle implicit sections.

    Instead of having the special list of implicit sections,
    that are mixed with the sections read from YAML on late
    stages, I just create the placeholders and add them to
    the main sections list early.

    That allows to significantly simplify the code.

    Differential revision: (detail/ViewSVN)
    by grimar
  17. [clangd] Set buffer name for main file. NFCI (detail/ViewSVN)
    by sammccall
  18. [clangd] Log input code of failed highlighting tests. NFC (detail/ViewSVN)
    by ibiryukov
  19. [AST] Treat semantic form of InitListExpr as implicit code in traversals

    In particular, do not traverse the semantic form if shouldVisitImplicitCode()
    returns false.

    This simplifies the common case of traversals, avoiding the need to
    worry about some expressions being traversed twice.

    No tests break after the change, the change would allow to simplify at
    least one of the usages, i.e. r366070 which had to handle this in

    Reviewers: gribozavr

    Reviewed By: gribozavr

    Subscribers: kadircet, cfe-commits

    Tags: #clang

    Differential Revision: (detail/ViewSVN)
    by ibiryukov

Started by upstream project clang-stage2-Rthinlto_relay build number 1896
originally caused by:

This run spent:

  • 1 hr 6 min waiting;
  • 5 hr 17 min build duration;
  • 6 hr 23 min total from scheduled to completion.
LLVM/Clang Warnings: 1 warning.
    Test Result (no failures)