1. [SelectionDAG][Mips][Sparc] Don't allow SimplifyDemandedBits to constant (details)
  2. [libTooling] Add `ifBound`, `elseBranch` RangeSelector combinators. (details)
  3. Doxygenify comments. (details)
  4. [MTE] Handle MTE instructions in AArch64LoadStoreOptimizer. (details)
  5. [NFC][InstCombine] Fixup newly-added tests (details)
Commit 1b7b4b467f03322f37b20ccee5cdef0c9ecec5d4 by craig.topper
[SelectionDAG][Mips][Sparc] Don't allow SimplifyDemandedBits to constant
fold TargetConstant nodes to a Constant.
Summary: After the switch in SimplifyDemandedBits, it tries to create a
constant when possible. If the original node is a TargetConstant the
default in the switch will call computeKnownBits on the TargetConstant
which will succeed. This results in the TargetConstant becoming a
Constant. But TargetConstant exists to avoid being changed.
I've fixed the two cases that relied on this in tree by explicitly
making the nodes constant instead of target constant. The Sparc case is
an old bug. The Mips case was recently introduced now that ImmArg on
intrinsics gets turned into a TargetConstant when the SelectionDAG is
created. I've removed the ImmArg since it lowers to generic code.
Reviewers: arsenm, RKSimon, spatel
Subscribers: jyknight, sdardis, wdng, arichardson, hiraditya,
fedor.sergeev, jrtc27, atanasyan, llvm-commits
Tags: #llvm
Differential Revision:
llvm-svn: 372409
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp (diff)
The file was modifiedllvm/include/llvm/IR/ (diff)
The file was modifiedllvm/lib/Target/Sparc/SparcISelLowering.cpp (diff)
Commit eff88e42f7860ac38cccafd175f5feca4d89c7c3 by yitzhakm
[libTooling] Add `ifBound`, `elseBranch` RangeSelector combinators.
Summary: Adds two new combinators and corresponding tests to the
RangeSelector library.
* `ifBound` -- conditional evaluation of range-selectors, based on
whether a
  given node id is bound in the match.
* `elseBranch` -- selects the source range of the else and its
Reviewers: gribozavr
Subscribers: cfe-commits
Tags: #clang
Differential Revision:
llvm-svn: 372410
The file was modifiedclang/lib/Tooling/Refactoring/RangeSelector.cpp (diff)
The file was modifiedclang/unittests/Tooling/RangeSelectorTest.cpp (diff)
The file was modifiedclang/include/clang/Tooling/Refactoring/RangeSelector.h (diff)
Commit 330014843ceccdcb32463875b3fcd36654e75ad4 by Adrian Prantl
Doxygenify comments.
llvm-svn: 372411
The file was modifiedlldb/source/Symbol/Variable.cpp (diff)
The file was modifiedlldb/include/lldb/Symbol/Variable.h (diff)
Commit c2bda3e422a9d00c49f4f3faf3adfb0ac9767097 by eugeni.stepanov
[MTE] Handle MTE instructions in AArch64LoadStoreOptimizer.
Summary: Generate pre- and post-indexed forms of ST*G and STGP when
Reviewers: ostannard, vitalybuka
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision:
llvm-svn: 372412
The file was addedllvm/test/CodeGen/AArch64/ldst-opt-mte.mir
The file was modifiedllvm/test/CodeGen/AArch64/stgp.ll (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp (diff)
Commit 081eebc58fcc9baa7517b20eb1243e0bf056a683 by lebedev.ri
[NFC][InstCombine] Fixup newly-added tests
llvm-svn: 372413
The file was modifiedllvm/test/Transforms/InstCombine/result-of-add-of-negative-is-non-zero-and-no-underflow.ll (diff)
The file was modifiedllvm/test/Transforms/InstCombine/result-of-add-of-negative-or-zero-is-non-zero-and-no-underflow.ll (diff)