FailedChanges

Summary

  1. [Dominators][CodeGen] Don't mark MachineDominatorTree as preserved in MachineLICM
  2. [Dominators][CodeGen] Fix MachineDominatorTree preservation in PHIElimination Summary: PHIElimination modifies CFG and marks MachineDominatorTree as preserved. Therefore, it the CFG changes it should also update the MDT, when available. This patch teaches PHIElimination to recalculate MDT when necessary. This fixes the `tailmerging_in_mbp.ll` test failure discovered after switching to generic DomTree verification algorithm in MachineDominators in D67976. Reviewers: arsenm, hliao, alex-t, rampitec, vpykhtin, grosser Reviewed By: rampitec Subscribers: MatzeB, wdng, hiraditya, javed.absar, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68154
  3. Reapply [Dominators][CodeGen] Clean up MachineDominators This reverts r373117 (git commit 159ef37735f21ae373282e0c53cbd9b6af1e0dfd) Phabricator review: https://reviews.llvm.org/D67976.
  4. [NFC] Updated tests after rL373371 Forgot to run check-clang-semacxx.
  5. [OPENMP]Fix PR43330: OpenMP target: Mapping of partial arrays fails. Fixed calculation the size of the array sections.
  6. [Diagnostics] Make -Wenum-compare-conditional off by default Too many false positives, eg. in Chromium.
  7. [ThinLTO] Enable index-only WPD from clang Summary: To trigger the index-only Whole Program Devirt support added to LLVM, we need to be able to specify -fno-split-lto-unit in conjunction with -fwhole-program-vtables. Keep the default for -fwhole-program-vtables as -fsplit-lto-unit, but don't error on that option combination. Reviewers: pcc Subscribers: mehdi_amini, inglorion, steven_wu, dexonsmith, arphaman, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D68029
  8. [PGO] Fix typos from r359612. NFC.
  9. [ARM] Some MVE shuffle plus extend tests. NFC
  10. Revert "compiler-rt: use __GLIBC_PREREQ for SANITIZER_INTERCEPT_GETRANDOM" Revert "compiler-rt: move all __GLIBC_PREREQ into own header file" "move all __GLIBC_PREREQ" breaks build on some bots This reverts commit 2d75ee937397c209dbd95aefc88da6301fed07da. This reverts commit 7a6461fcc2ed8e28c43993c561721af0bbe97f3a.
  11. AMDGPU/SILoadStoreOptimizer: Add helper functions for working with CombineInfo Summary: This is a refactoring that will make future improvements to this pass easier. This change should not change the behavior of the pass. Reviewers: arsenm, pendingchaos, rampitec, nhaehnle, vpykhtin Reviewed By: nhaehnle, vpykhtin Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65496
  12. [InstCombine] Deal with -(trunc(X >>u 63)) -> trunc(X >>s 63) Identical to it's trunc-less variant, just pretent-to hoist trunc, and everything else still holds: https://rise4fun.com/Alive/JRU
  13. [InstCombine] Preserve 'exact' in -(X >>u 31) -> (X >>s 31) fold https://rise4fun.com/Alive/yR4
  14. [NFC][InstCombine] (Better) tests for sign-bit-smearing pattern https://rise4fun.com/Alive/JRU https://rise4fun.com/Alive/yR4 <- we can preserve 'exact'
  15. [llvm-mca] Add a -mattr flag This adds a -mattr flag to llvm-mca, for cases where the -mcpu option does not contain all optional features. Differential Revision: https://reviews.llvm.org/D68190
  16. [ReleaseProcess] Document requirement to set MACOSX_DEPLOYMENT_TARGET
  17. [IndVars] An implementation of loop predication without a need for speculation This patch implements a variation of a well known techniques for JIT compilers - we have an implementation in tree as LoopPredication - but with an interesting twist. This version does not assume the ability to execute a path which wasn't taken in the original program (such as a guard or widenable.condition intrinsic). The benefit is that this works for arbitrary IR from any frontend (including C/C++/Fortran). The tradeoff is that it's restricted to read only loops without implicit exits. This builds on SCEV, and can thus eliminate the loop varying portion of the any early exit where all exits are understandable by SCEV. A key advantage is that fixing deficiency exposed in SCEV - already found one while writing test cases - will also benefit all of full redundancy elimination (and most other loop transforms). I haven't seen anything in the literature which quite matches this. Given that, I'm not entirely sure that keeping the name "loop predication" is helpful. Anyone have suggestions for a better name? This is analogous to partial redundancy elimination - since we remove the condition flowing around the backedge - and has some parallels to our existing transforms which try to make conditions invariant in loops. Factoring wise, I chose to put this in IndVarSimplify since it's a generally applicable to all workloads. I could split this off into it's own pass, but we'd then probably want to add that new pass every place we use IndVars. One solid argument for splitting it off into it's own pass is that this transform is "too good". It breaks a huge number of existing IndVars test cases as they tend to be simple read only loops. At the moment, I've opted it off by default, but if we add this to IndVars and enable, we'll have to update around 20 test files to add side effects or disable this transform. Near term plan is to fuzz this extensively while off by default, reflect and discuss on the factoring issue mentioned just above, and then enable by default. I also need to give some though to supporting widenable conditions in this framing. Differential Revision: https://reviews.llvm.org/D67408
  18. AMDGPU/GlobalISel: Increase max legal size to 1024 There are 1024 bit register classes defined for AGPRs. Additionally OpenCL defines vectors up to 16 x i64, and this helps those tests legalize.
  19. [X86] Add a VBROADCAST_LOAD ISD opcode representing a scalar load broadcasted to a vector. Summary: This adds the ISD opcode and a DAG combine to create it. There are probably some places where we can directly create it, but I'll leave that for future work. This updates all of the isel patterns to look for this new node. I had to add a few additional isel patterns for aligned extloads which we should probably fix with a DAG combine or something. This does mean that the broadcast load folding for avx512 can no longer match a broadcasted aligned extload. There's still some work to do here for combining a broadcast of a broadcast_load. We also need to improve extractelement or demanded vector elements of a broadcast_load. I'll try to get those done before I submit this patch. Reviewers: RKSimon, spatel Reviewed By: RKSimon Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68198
  20. [OPENMP]Fix PR43516: Compiler crash with collapse(2) on non-rectangular loop. Missed check if the condition is also dependent when building final expressions for the collapsed loop directives.
  21. [AMDGPU] Add VerifyScheduling support. Summary: This is cut and pasted from the corresponding GenericScheduler functions. Reviewers: arsenm, atrick, tstellar, vpykhtin Subscribers: MatzeB, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, javed.absar, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68264
  22. [Diagnostics] Move warning into the subgroup (-Wenum-compare-conditional)
  23. [DAG][X86] Convert isNegatibleForFree/GetNegatedExpression to a target hook (PR42863) This patch converts the DAGCombine isNegatibleForFree/GetNegatedExpression into overridable TLI hooks. The intention is to let us extend existing FNEG combines to work more generally with negatible float ops, allowing it work with target specific combines and opcodes (e.g. X86's FMA variants). Unlike the SimplifyDemandedBits, we can't just handle target nodes through a Target callback, we need to do this as an override to allow targets to handle generic opcodes as well. This does mean that the target implementations has to duplicate some checks (recursion depth etc.). Partial reversion of rL372756 - I've identified the infinite loop issue inside the X86 override but haven't fixed it yet so I've only (re)committed the common TargetLowering refactoring part of the patch. Differential Revision: https://reviews.llvm.org/D67557
  24. [Dominators][CodeGen] Add MachinePostDominatorTree verification Summary: This patch implements Machine PostDominator Tree verification and ensures that the verification doesn't fail the in-tree tests. MPDT verification can be enabled using `verify-machine-dom-info` -- the same flag used by Machine Dominator Tree verification. Flipping the flag revealed that MachineSink falsely claimed to preserve CFG and MDT/MPDT. This patch fixes that. Reviewers: arsenm, hliao, rampitec, vpykhtin, grosser Reviewed By: hliao Subscribers: wdng, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68235
Revision 373378 by kuhar:
[Dominators][CodeGen] Don't mark MachineDominatorTree as preserved in MachineLICM
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/MachineLICM.cppllvm.src/lib/CodeGen/MachineLICM.cpp
The file was modified/llvm/trunk/test/CodeGen/AArch64/O3-pipeline.llllvm.src/test/CodeGen/AArch64/O3-pipeline.ll
The file was modified/llvm/trunk/test/CodeGen/ARM/O3-pipeline.llllvm.src/test/CodeGen/ARM/O3-pipeline.ll
The file was modified/llvm/trunk/test/CodeGen/X86/O3-pipeline.llllvm.src/test/CodeGen/X86/O3-pipeline.ll
Revision 373377 by kuhar:
[Dominators][CodeGen] Fix MachineDominatorTree preservation in PHIElimination

Summary:
PHIElimination modifies CFG and marks MachineDominatorTree as preserved. Therefore, it the CFG changes it should also update the MDT, when available. This patch teaches PHIElimination to recalculate MDT when necessary.

This fixes the `tailmerging_in_mbp.ll` test failure discovered after switching to generic DomTree verification algorithm in MachineDominators in D67976.

Reviewers: arsenm, hliao, alex-t, rampitec, vpykhtin, grosser

Reviewed By: rampitec

Subscribers: MatzeB, wdng, hiraditya, javed.absar, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68154
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/MachineScheduler.cppllvm.src/lib/CodeGen/MachineScheduler.cpp
The file was modified/llvm/trunk/lib/CodeGen/PHIElimination.cppllvm.src/lib/CodeGen/PHIElimination.cpp
Revision 373376 by kuhar:
Reapply [Dominators][CodeGen] Clean up MachineDominators

This reverts r373117 (git commit 159ef37735f21ae373282e0c53cbd9b6af1e0dfd)

Phabricator review: https://reviews.llvm.org/D67976.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/MachineDominators.hllvm.src/include/llvm/CodeGen/MachineDominators.h
The file was modified/llvm/trunk/lib/CodeGen/MachineDominators.cppllvm.src/lib/CodeGen/MachineDominators.cpp
Revision 373375 by xbolva00:
[NFC] Updated tests after rL373371

Forgot to run check-clang-semacxx.
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/test/SemaCXX/warn-sign-conversion.cppclang.src/test/SemaCXX/warn-sign-conversion.cpp
Revision 373374 by abataev:
[OPENMP]Fix PR43330: OpenMP target: Mapping of partial arrays fails.

Fixed calculation the size of the array sections.
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/lib/CodeGen/CGOpenMPRuntime.cppclang.src/lib/CodeGen/CGOpenMPRuntime.cpp
The file was modified/cfe/trunk/test/OpenMP/target_map_codegen.cppclang.src/test/OpenMP/target_map_codegen.cpp
Revision 373371 by xbolva00:
[Diagnostics] Make -Wenum-compare-conditional off by default

Too many false positives, eg. in Chromium.
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/include/clang/Basic/DiagnosticGroups.tdclang.src/include/clang/Basic/DiagnosticGroups.td
The file was modified/cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.tdclang.src/include/clang/Basic/DiagnosticSemaKinds.td
The file was modified/cfe/trunk/test/Sema/warn-conditional-emum-types-mismatch.cclang.src/test/Sema/warn-conditional-emum-types-mismatch.c
Revision 373370 by tejohnson:
[ThinLTO] Enable index-only WPD from clang

Summary:
To trigger the index-only Whole Program Devirt support added to LLVM, we
need to be able to specify -fno-split-lto-unit in conjunction with
-fwhole-program-vtables. Keep the default for -fwhole-program-vtables as
-fsplit-lto-unit, but don't error on that option combination.

Reviewers: pcc

Subscribers: mehdi_amini, inglorion, steven_wu, dexonsmith, arphaman, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D68029
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/lib/Driver/ToolChains/Clang.cppclang.src/lib/Driver/ToolChains/Clang.cpp
The file was modified/cfe/trunk/test/Driver/split-lto-unit.cclang.src/test/Driver/split-lto-unit.c
Revision 373369 by xur:
[PGO] Fix typos from r359612. NFC.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/ProfileData/InstrProf.hllvm.src/include/llvm/ProfileData/InstrProf.h
The file was modified/llvm/trunk/include/llvm/ProfileData/InstrProfReader.hllvm.src/include/llvm/ProfileData/InstrProfReader.h
The file was modified/llvm/trunk/lib/ProfileData/InstrProf.cppllvm.src/lib/ProfileData/InstrProf.cpp
The file was modified/llvm/trunk/lib/ProfileData/InstrProfReader.cppllvm.src/lib/ProfileData/InstrProfReader.cpp
The file was modified/llvm/trunk/lib/ProfileData/InstrProfWriter.cppllvm.src/lib/ProfileData/InstrProfWriter.cpp
The file was modified/llvm/trunk/tools/llvm-profdata/llvm-profdata.cppllvm.src/tools/llvm-profdata/llvm-profdata.cpp
Revision 373368 by dmgreen:
[ARM] Some MVE shuffle plus extend tests. NFC
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/test/CodeGen/Thumb2/mve-shuffleext.llllvm.src/test/CodeGen/Thumb2/mve-shuffleext.ll
Revision 373367 by Vitaly Buka:
Revert "compiler-rt: use __GLIBC_PREREQ for SANITIZER_INTERCEPT_GETRANDOM"
Revert "compiler-rt: move all __GLIBC_PREREQ into own header file"

"move all __GLIBC_PREREQ" breaks build on some bots

This reverts commit 2d75ee937397c209dbd95aefc88da6301fed07da.
This reverts commit 7a6461fcc2ed8e28c43993c561721af0bbe97f3a.
Change TypePath in RepositoryPath in Workspace
The file was modified/compiler-rt/trunk/lib/sanitizer_common/sanitizer_getauxval.hcompiler-rt.src/lib/sanitizer_common/sanitizer_getauxval.h
The file was removed/compiler-rt/trunk/lib/sanitizer_common/sanitizer_glibc_version.hcompiler-rt.src/lib/sanitizer_common/sanitizer_glibc_version.h
The file was modified/compiler-rt/trunk/lib/sanitizer_common/sanitizer_linux_libcdep.cppcompiler-rt.src/lib/sanitizer_common/sanitizer_linux_libcdep.cpp
The file was modified/compiler-rt/trunk/lib/sanitizer_common/sanitizer_platform_interceptors.hcompiler-rt.src/lib/sanitizer_common/sanitizer_platform_interceptors.h
The file was modified/compiler-rt/trunk/lib/sanitizer_common/sanitizer_platform_limits_posix.cppcompiler-rt.src/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp
The file was modified/compiler-rt/trunk/lib/sanitizer_common/sanitizer_platform_limits_posix.hcompiler-rt.src/lib/sanitizer_common/sanitizer_platform_limits_posix.h
Revision 373366 by tstellar:
AMDGPU/SILoadStoreOptimizer: Add helper functions for working with CombineInfo

Summary:
This is a refactoring that will make future improvements to this pass easier.
This change should not change the behavior of the pass.

Reviewers: arsenm, pendingchaos, rampitec, nhaehnle, vpykhtin

Reviewed By: nhaehnle, vpykhtin

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65496
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cppllvm.src/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
Revision 373364 by lebedevri:
[InstCombine] Deal with -(trunc(X >>u 63)) -> trunc(X >>s 63)

Identical to it's trunc-less variant, just pretent-to hoist
trunc, and everything else still holds:
https://rise4fun.com/Alive/JRU
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineAddSub.cppllvm.src/lib/Transforms/InstCombine/InstCombineAddSub.cpp
The file was modified/llvm/trunk/test/Transforms/InstCombine/high-bit-signmask-with-trunc.llllvm.src/test/Transforms/InstCombine/high-bit-signmask-with-trunc.ll
Revision 373363 by lebedevri:
[InstCombine] Preserve 'exact' in -(X >>u 31) -> (X >>s 31) fold

https://rise4fun.com/Alive/yR4
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineAddSub.cppllvm.src/lib/Transforms/InstCombine/InstCombineAddSub.cpp
The file was modified/llvm/trunk/test/Transforms/InstCombine/high-bit-signmask.llllvm.src/test/Transforms/InstCombine/high-bit-signmask.ll
Revision 373362 by lebedevri:
[NFC][InstCombine] (Better) tests for sign-bit-smearing pattern

https://rise4fun.com/Alive/JRU
https://rise4fun.com/Alive/yR4 <- we can preserve 'exact'
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/test/Transforms/InstCombine/high-bit-signmask-with-trunc.llllvm.src/test/Transforms/InstCombine/high-bit-signmask-with-trunc.ll
The file was added/llvm/trunk/test/Transforms/InstCombine/high-bit-signmask.llllvm.src/test/Transforms/InstCombine/high-bit-signmask.ll
Revision 373358 by dmgreen:
[llvm-mca] Add a -mattr flag

This adds a -mattr flag to llvm-mca, for cases where the -mcpu option does not
contain all optional features.

Differential Revision: https://reviews.llvm.org/D68190
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/test/tools/llvm-mca/ARM/m4-targetfeatures.sllvm.src/test/tools/llvm-mca/ARM/m4-targetfeatures.s
The file was modified/llvm/trunk/tools/llvm-mca/llvm-mca.cppllvm.src/tools/llvm-mca/llvm-mca.cpp
Revision 373356 by Vedant Kumar:
[ReleaseProcess] Document requirement to set MACOSX_DEPLOYMENT_TARGET
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/docs/ReleaseProcess.rstllvm.src/docs/ReleaseProcess.rst
Revision 373351 by reames:
[IndVars] An implementation of loop predication without a need for speculation

This patch implements a variation of a well known techniques for JIT compilers - we have an implementation in tree as LoopPredication - but with an interesting twist. This version does not assume the ability to execute a path which wasn't taken in the original program (such as a guard or widenable.condition intrinsic). The benefit is that this works for arbitrary IR from any frontend (including C/C++/Fortran). The tradeoff is that it's restricted to read only loops without implicit exits.

This builds on SCEV, and can thus eliminate the loop varying portion of the any early exit where all exits are understandable by SCEV. A key advantage is that fixing deficiency exposed in SCEV - already found one while writing test cases - will also benefit all of full redundancy elimination (and most other loop transforms).

I haven't seen anything in the literature which quite matches this. Given that, I'm not entirely sure that keeping the name "loop predication" is helpful. Anyone have suggestions for a better name? This is analogous to partial redundancy elimination - since we remove the condition flowing around the backedge - and has some parallels to our existing transforms which try to make conditions invariant in loops.

Factoring wise, I chose to put this in IndVarSimplify since it's a generally applicable to all workloads. I could split this off into it's own pass, but we'd then probably want to add that new pass every place we use IndVars.  One solid argument for splitting it off into it's own pass is that this transform is "too good". It breaks a huge number of existing IndVars test cases as they tend to be simple read only loops.  At the moment, I've opted it off by default, but if we add this to IndVars and enable, we'll have to update around 20 test files to add side effects or disable this transform.

Near term plan is to fuzz this extensively while off by default, reflect and discuss on the factoring issue mentioned just above, and then enable by default.  I also need to give some though to supporting widenable conditions in this framing.

Differential Revision: https://reviews.llvm.org/D67408
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cppllvm.src/lib/Transforms/Scalar/IndVarSimplify.cpp
The file was added/llvm/trunk/test/Transforms/IndVarSimplify/loop-predication.llllvm.src/test/Transforms/IndVarSimplify/loop-predication.ll
Revision 373350 by arsenm:
AMDGPU/GlobalISel: Increase max legal size to 1024

There are 1024 bit register classes defined for AGPRs. Additionally
OpenCL defines vectors up to 16 x i64, and this helps those tests
legalize.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cppllvm.src/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBanks.tdllvm.src/lib/Target/AMDGPU/AMDGPURegisterBanks.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cppllvm.src/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
Revision 373349 by ctopper:
[X86] Add a VBROADCAST_LOAD ISD opcode representing a scalar load broadcasted to a vector.

Summary:
This adds the ISD opcode and a DAG combine to create it. There are
probably some places where we can directly create it, but I'll
leave that for future work.

This updates all of the isel patterns to look for this new node.
I had to add a few additional isel patterns for aligned extloads
which we should probably fix with a DAG combine or something. This
does mean that the broadcast load folding for avx512 can no
longer match a broadcasted aligned extload.

There's still some work to do here for combining a broadcast of
a broadcast_load. We also need to improve extractelement or
demanded vector elements of a broadcast_load. I'll try to get
those done before I submit this patch.

Reviewers: RKSimon, spatel

Reviewed By: RKSimon

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68198
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cppllvm.src/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cppllvm.src/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.hllvm.src/lib/Target/X86/X86ISelLowering.h
The file was modified/llvm/trunk/lib/Target/X86/X86InstrAVX512.tdllvm.src/lib/Target/X86/X86InstrAVX512.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.tdllvm.src/lib/Target/X86/X86InstrFragmentsSIMD.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrSSE.tdllvm.src/lib/Target/X86/X86InstrSSE.td
The file was modified/llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.llllvm.src/test/CodeGen/X86/avx512-intrinsics-upgrade.ll
The file was modified/llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-upgrade.llllvm.src/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
The file was modified/llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.llllvm.src/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll
The file was modified/llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics-upgrade.llllvm.src/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
The file was modified/llvm/trunk/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.llllvm.src/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
Revision 373348 by abataev:
[OPENMP]Fix PR43516: Compiler crash with collapse(2) on non-rectangular
loop.

Missed check if the condition is also dependent when building final
expressions for the collapsed loop directives.
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/lib/Sema/SemaOpenMP.cppclang.src/lib/Sema/SemaOpenMP.cpp
The file was modified/cfe/trunk/test/OpenMP/for_codegen.cppclang.src/test/OpenMP/for_codegen.cpp
Revision 373346 by foad:
[AMDGPU] Add VerifyScheduling support.

Summary:
This is cut and pasted from the corresponding GenericScheduler
functions.

Reviewers: arsenm, atrick, tstellar, vpykhtin

Subscribers: MatzeB, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, javed.absar, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68264
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/MachineScheduler.hllvm.src/include/llvm/CodeGen/MachineScheduler.h
The file was modified/llvm/trunk/lib/CodeGen/MachineScheduler.cppllvm.src/lib/CodeGen/MachineScheduler.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/GCNSchedStrategy.cppllvm.src/lib/Target/AMDGPU/GCNSchedStrategy.cpp
Revision 373345 by xbolva00:
[Diagnostics] Move warning into the subgroup (-Wenum-compare-conditional)
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/include/clang/Basic/DiagnosticGroups.tdclang.src/include/clang/Basic/DiagnosticGroups.td
The file was modified/cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.tdclang.src/include/clang/Basic/DiagnosticSemaKinds.td
The file was modified/cfe/trunk/test/Sema/warn-conditional-emum-types-mismatch.cclang.src/test/Sema/warn-conditional-emum-types-mismatch.c
Revision 373343 by rksimon:
[DAG][X86] Convert isNegatibleForFree/GetNegatedExpression to a target hook (PR42863)

This patch converts the DAGCombine isNegatibleForFree/GetNegatedExpression into overridable TLI hooks.

The intention is to let us extend existing FNEG combines to work more generally with negatible float ops, allowing it work with target specific combines and opcodes (e.g. X86's FMA variants).

Unlike the SimplifyDemandedBits, we can't just handle target nodes through a Target callback, we need to do this as an override to allow targets to handle generic opcodes as well. This does mean that the target implementations has to duplicate some checks (recursion depth etc.).

Partial reversion of rL372756 - I've identified the infinite loop issue inside the X86 override but haven't fixed it yet so I've only (re)committed the common TargetLowering refactoring part of the patch.

Differential Revision: https://reviews.llvm.org/D67557
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/TargetLowering.hllvm.src/include/llvm/CodeGen/TargetLowering.h
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cppllvm.src/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cppllvm.src/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Revision 373341 by kuhar:
[Dominators][CodeGen] Add MachinePostDominatorTree verification

Summary:
This patch implements Machine PostDominator Tree verification and ensures that the verification doesn't fail the in-tree tests.

MPDT verification can be enabled using `verify-machine-dom-info` -- the same flag used by Machine Dominator Tree verification.

Flipping the flag revealed that MachineSink falsely claimed to preserve CFG and MDT/MPDT. This patch fixes that.

Reviewers: arsenm, hliao, rampitec, vpykhtin, grosser

Reviewed By: hliao

Subscribers: wdng, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68235
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/MachinePostDominators.hllvm.src/include/llvm/CodeGen/MachinePostDominators.h
The file was modified/llvm/trunk/lib/CodeGen/MachineDominators.cppllvm.src/lib/CodeGen/MachineDominators.cpp
The file was modified/llvm/trunk/lib/CodeGen/MachinePostDominators.cppllvm.src/lib/CodeGen/MachinePostDominators.cpp
The file was modified/llvm/trunk/lib/CodeGen/MachineSink.cppllvm.src/lib/CodeGen/MachineSink.cpp
The file was modified/llvm/trunk/test/CodeGen/AArch64/O3-pipeline.llllvm.src/test/CodeGen/AArch64/O3-pipeline.ll