FailedChanges

Summary

  1. [X86][SSE] resolveTargetShuffleInputs - call getTargetShuffleInputs instead of using setTargetShuffleZeroElements directly. NFCI.
  2. [Docs] Adds new Getting Started/Tutorials page Adds a new page for Getting Started/Tutorials topics. Also updates existing topic categories on the User Guides and Reference pages.
  3. Revert [DAGCombine] Match more patterns for half word bswap This reverts r373850 (git commit 25ba49824d2d4f2347b4a7cb1623600a76ce9433) This patch appears to cause multiple codegen regression test failures - http://lab.llvm.org:8011/builders/clang-cmake-armv7-quick/builds/10680
  4. [NFC] Replace 'isDarwin' with 'IsDarwin' Summary: Replace 'isDarwin' with 'IsDarwin' based on LLVM naming convention. Differential Revision: https://reviews.llvm.org/D68336
  5. [InstCombine] fold fneg disguised as select+fmul (PR43497) Extends rL373230 and solves the motivating bug (although in a narrow way): https://bugs.llvm.org/show_bug.cgi?id=43497
  6. [DAGCombine] Match more patterns for half word bswap Summary: It ensures that the bswap is generated even when a part of the subtree already matches a bswap transform. Reviewers: craig.topper, efriedma, RKSimon, lebedev.ri Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68250
  7. [X86][AVX] combineExtractSubvector - merge duplicate variables. NFCI.
  8. [InstCombine] add fast-math-flags for better test coverage; NFC
  9. [InstCombine] don't assume 'inbounds' for bitcast pointer to GEP transform (PR43501) https://bugs.llvm.org/show_bug.cgi?id=43501 We can't declare a GEP 'inbounds' in general. But we may salvage that information if we have known dereferenceable bytes on the source pointer. Differential Revision: https://reviews.llvm.org/D68244
  10. [X86][SSE] matchVectorShuffleAsBlend - use Zeroable element mask directly. We can make use of the Zeroable mask to indicate which elements we can safely set to zero instead of creating a target shuffle mask on the fly. This allows us to remove createTargetShuffleMask. This is part of the work to fix PR43024 and allow us to use SimplifyDemandedElts to simplify shuffle chains - we need to get to a point where the target shuffle masks isn't adjusted by its source inputs in setTargetShuffleZeroElements but instead we cache them in a parallel Zeroable mask.
Revision 373855 by rksimon:
[X86][SSE] resolveTargetShuffleInputs - call getTargetShuffleInputs instead of using setTargetShuffleZeroElements directly. NFCI.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cppllvm.src/lib/Target/X86/X86ISelLowering.cpp
Revision 373854 by dr87:
[Docs] Adds new Getting Started/Tutorials page

Adds a new page for Getting Started/Tutorials topics. Also updates existing topic categories on the User Guides and Reference pages.
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/docs/GettingStartedTutorials.rstllvm.src/docs/GettingStartedTutorials.rst
The file was modified/llvm/trunk/docs/ProgrammingDocumentation.rstllvm.src/docs/ProgrammingDocumentation.rst
The file was modified/llvm/trunk/docs/Reference.rstllvm.src/docs/Reference.rst
The file was modified/llvm/trunk/docs/SubsystemDocumentation.rstllvm.src/docs/SubsystemDocumentation.rst
The file was modified/llvm/trunk/docs/UserGuides.rstllvm.src/docs/UserGuides.rst
The file was modified/llvm/trunk/docs/index.rstllvm.src/docs/index.rst
Revision 373853 by spatel:
Revert [DAGCombine] Match more patterns for half word bswap

This reverts r373850 (git commit 25ba49824d2d4f2347b4a7cb1623600a76ce9433)

This patch appears to cause multiple codegen regression test failures - http://lab.llvm.org:8011/builders/clang-cmake-armv7-quick/builds/10680
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cppllvm.src/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/bswap_tree.llllvm.src/test/CodeGen/X86/bswap_tree.ll
Revision 373852 by xiangling_liao:
[NFC] Replace 'isDarwin' with 'IsDarwin'

Summary: Replace 'isDarwin' with 'IsDarwin' based on LLVM naming convention.

Differential Revision: https://reviews.llvm.org/D68336
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.cppllvm.src/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.hllvm.src/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.h
The file was modified/llvm/trunk/lib/Target/PowerPC/PPC.hllvm.src/lib/Target/PowerPC/PPC.h
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cppllvm.src/lib/Target/PowerPC/PPCAsmPrinter.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cppllvm.src/lib/Target/PowerPC/PPCFrameLowering.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cppllvm.src/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCMCInstLower.cppllvm.src/lib/Target/PowerPC/PPCMCInstLower.cpp
Revision 373851 by spatel:
[InstCombine] fold fneg disguised as select+fmul (PR43497)

Extends rL373230 and solves the motivating bug (although in a narrow way):
https://bugs.llvm.org/show_bug.cgi?id=43497
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cppllvm.src/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
The file was modified/llvm/trunk/test/Transforms/InstCombine/fmul.llllvm.src/test/Transforms/InstCombine/fmul.ll
Revision 373850 by deadalnix:
[DAGCombine] Match more patterns for half word bswap

Summary: It ensures that the bswap is generated even when a part of the subtree already matches a bswap transform.

Reviewers: craig.topper, efriedma, RKSimon, lebedev.ri

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68250
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cppllvm.src/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/bswap_tree.llllvm.src/test/CodeGen/X86/bswap_tree.ll
Revision 373849 by rksimon:
[X86][AVX] combineExtractSubvector - merge duplicate variables. NFCI.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cppllvm.src/lib/Target/X86/X86ISelLowering.cpp
Revision 373848 by spatel:
[InstCombine] add fast-math-flags for better test coverage; NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/InstCombine/fmul.llllvm.src/test/Transforms/InstCombine/fmul.ll
Revision 373847 by spatel:
[InstCombine] don't assume 'inbounds' for bitcast pointer to GEP transform (PR43501)

https://bugs.llvm.org/show_bug.cgi?id=43501
We can't declare a GEP 'inbounds' in general. But we may salvage that information if
we have known dereferenceable bytes on the source pointer.

Differential Revision: https://reviews.llvm.org/D68244
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/test/CodeGen/aapcs-bitfield.cclang.src/test/CodeGen/aapcs-bitfield.c
The file was modified/cfe/trunk/test/CodeGenCXX/microsoft-abi-dynamic-cast.cppclang.src/test/CodeGenCXX/microsoft-abi-dynamic-cast.cpp
The file was modified/cfe/trunk/test/CodeGenCXX/microsoft-abi-typeid.cppclang.src/test/CodeGenCXX/microsoft-abi-typeid.cpp
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cppllvm.src/lib/Transforms/InstCombine/InstCombineCasts.cpp
The file was modified/llvm/trunk/test/Transforms/InstCombine/addrspacecast.llllvm.src/test/Transforms/InstCombine/addrspacecast.ll
The file was modified/llvm/trunk/test/Transforms/InstCombine/cast.llllvm.src/test/Transforms/InstCombine/cast.ll
The file was modified/llvm/trunk/test/Transforms/InstCombine/load-bitcast-vec.llllvm.src/test/Transforms/InstCombine/load-bitcast-vec.ll
The file was modified/llvm/trunk/test/Transforms/InstCombine/memset.llllvm.src/test/Transforms/InstCombine/memset.ll
The file was modified/llvm/trunk/test/Transforms/InstCombine/unpack-fca.llllvm.src/test/Transforms/InstCombine/unpack-fca.ll
Revision 373846 by rksimon:
[X86][SSE] matchVectorShuffleAsBlend - use Zeroable element mask directly.

We can make use of the Zeroable mask to indicate which elements we can safely set to zero instead of creating a target shuffle mask on the fly.

This allows us to remove createTargetShuffleMask.

This is part of the work to fix PR43024 and allow us to use SimplifyDemandedElts to simplify shuffle chains - we need to get to a point where the target shuffle masks isn't adjusted by its source inputs in setTargetShuffleZeroElements but instead we cache them in a parallel Zeroable mask.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cppllvm.src/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/packss.llllvm.src/test/CodeGen/X86/packss.ll