FailedChanges

Summary

  1. [AArch64] Adding support for PMMIR_EL1 register Summary: The PMMIR_EL1 register is present in Armv8.4 with PMU extension. This patch adds support for it. Reviewers: t.p.northover, dnsampaio Reviewed By: dnsampaio Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68940
  2. [clangd] Report declaration references in findExplicitReferences. Reviewers: ilya-biryukov Subscribers: MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D68977
  3. [ThinLTOCodeGenerator] Add support for index-based WPD This is clang part of the patch. It adds -flto-unit flag for thin LTO builds on Mac and PS4 Differential revision: https://reviews.llvm.org/D68950
  4. [AArch64][SVE] Add SPLAT_VECTOR ISD Node Adds a new ISD node to replicate a scalar value across all elements of a vector. This is needed for scalable vectors, since BUILD_VECTOR cannot be used. Fixes up default type legalization for scalable vectors after the new MVT type ranges were introduced. At present I only use this node for scalable vectors. A DAGCombine has been added to transform a BUILD_VECTOR into a SPLAT_VECTOR if all elements are the same, but only if the default operation action of Expand has been overridden by the target. I've only added result promotion legalization for scalable vector i8/i16/i32/i64 types in AArch64 for now. Reviewers: t.p.northover, javed.absar, greened, cameron.mcinally, jmolloy Reviewed By: jmolloy Differential Revision: https://reviews.llvm.org/D47775
  5. [Arm][libsanitizer] Fix arm libsanitizer failure with bleeding edge glibc Glibc has recently introduced changed to the mode field in ipc_perm in commit 2f959dfe849e0646e27403f2e4091536496ac0f0. For Arm this means that the mode field no longer has the same size. This causes an assert failure against libsanitizer's internal copy of ipc_perm. Since this change can't be easily detected I am adding arm to the list of targets that are excluded from this check. Patch by: Tamar Christina Differential Revision: https://reviews.llvm.org/D69104
  6. [ThinLTOCodeGenerator] Add support for index-based WPD Differential revision: https://reviews.llvm.org/D68950
  7. [AArch64] Don't combine callee-save and local stack adjustment when optimizing for size For arm64, D18619 introduced the ability to combine bumping the stack pointer upfront in case it needs to be bumped for both the callee-save area as well as the local stack area. That diff already remarks that "This change can cause an increase in instructions", but argues that even when that happens, it should be still be a performance benefit because the number of micro-ops is reduced. We have observed that this code-size increase can be significant in practice. This diff disables combining stack bumping for methods that are marked as optimize-for-size. Example of a prologue with the behavior before this diff (combining stack bumping when possible): sub sp, sp, #0x40 stp d9, d8, [sp, #0x10] stp x20, x19, [sp, #0x20] stp x29, x30, [sp, #0x30] add x29, sp, #0x30 [... compute x8 somehow ...] stp x0, x8, [sp] And after this diff, if the method is marked as optimize-for-size: stp d9, d8, [sp, #-0x30]! stp x20, x19, [sp, #0x10] stp x29, x30, [sp, #0x20] add x29, sp, #0x20 [... compute x8 somehow ...] stp x0, x8, [sp, #-0x10]! Note that without combining the stack bump there are two auto-decrements, nicely folded into the stp instructions, whereas otherwise there is a single sub sp, ... instruction, but not folded. Patch by Nikolai Tillmann! Differential Revision: https://reviews.llvm.org/D68530
  8. [X86] Regenerate memcmp tests and add X64-AVX512 common prefix Should help make the changes in D69157 clearer
  9. Fix MSVC "not all control paths return a value" warning. NFCI.
  10. Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warnings. NFCI.
  11. Remove -DLLVM_USE_LINKER from Windows self host bots. LLVM_USE_LINKER sets the -fuse-ld. This is redundant as the linker is set to lld-link. Differential Revision: https://reviews.llvm.org/D69098
  12. [Codegen] Alter the default promotion for saturating adds and subs The default promotion for the add_sat/sub_sat nodes currently does: ANY_EXTEND iN to iM SHL by M-N [US][ADD|SUB]SAT L/ASHR by M-N If the promoted add_sat or sub_sat node is not legal, this can produce code that effectively does a lot of shifting (and requiring large constants to be materialised) just to use the overflow flag. It is simpler to just do the saturation manually, using the higher bitwidth addition and a min/max against the saturating bounds. That is what this patch attempts to do. Differential Revision: https://reviews.llvm.org/D68926
  13. [AArch64][SVE] Implement unpack intrinsics Summary: Implements the following intrinsics: - int_aarch64_sve_sunpkhi - int_aarch64_sve_sunpklo - int_aarch64_sve_uunpkhi - int_aarch64_sve_uunpklo This patch also adds AArch64ISD nodes for UNPK instead of implementing the intrinsics directly, as they are required for a future patch which implements the sign/zero extension of legal vectors. This patch includes tests for the Subdivide2Argument type added by D67549 Reviewers: sdesmalen, SjoerdMeijer, greened, rengolin, rovka Reviewed By: greened Subscribers: tschuett, kristof.beyls, rkruppe, psnobl, cfe-commits, llvm-commits Differential Revision: https://reviews.llvm.org/D67550
Revision 375228 by vhscampos:
[AArch64] Adding support for PMMIR_EL1 register

Summary:
The PMMIR_EL1 register is present in Armv8.4 with PMU extension.
This patch adds support for it.

Reviewers: t.p.northover, dnsampaio

Reviewed By: dnsampaio

Subscribers: kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68940
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64.tdllvm.src/lib/Target/AArch64/AArch64.td
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.tdllvm.src/lib/Target/AArch64/AArch64InstrInfo.td
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.hllvm.src/lib/Target/AArch64/AArch64Subtarget.h
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.tdllvm.src/lib/Target/AArch64/AArch64SystemOperands.td
The file was added/llvm/trunk/test/MC/AArch64/armv8.4a-pmu.sllvm.src/test/MC/AArch64/armv8.4a-pmu.s
The file was added/llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-pmu.txtllvm.src/test/MC/Disassembler/AArch64/armv8.4a-pmu.txt
Revision 375226 by hokein:
[clangd] Report declaration references in findExplicitReferences.

Reviewers: ilya-biryukov

Subscribers: MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D68977
Change TypePath in RepositoryPath in Workspace
The file was modified/clang-tools-extra/trunk/clangd/AST.cppclang-tools-extra.src/clangd/AST.cpp
The file was modified/clang-tools-extra/trunk/clangd/AST.hclang-tools-extra.src/clangd/AST.h
The file was modified/clang-tools-extra/trunk/clangd/FindTarget.cppclang-tools-extra.src/clangd/FindTarget.cpp
The file was modified/clang-tools-extra/trunk/clangd/FindTarget.hclang-tools-extra.src/clangd/FindTarget.h
The file was modified/clang-tools-extra/trunk/clangd/XRefs.cppclang-tools-extra.src/clangd/XRefs.cpp
The file was modified/clang-tools-extra/trunk/clangd/unittests/FindTargetTests.cppclang-tools-extra.src/clangd/unittests/FindTargetTests.cpp
The file was modified/clang-tools-extra/trunk/clangd/unittests/XRefsTests.cppclang-tools-extra.src/clangd/unittests/XRefsTests.cpp
Revision 375224 by evgeny777:
[ThinLTOCodeGenerator] Add support for index-based WPD

This is clang part of the patch. It adds -flto-unit flag for thin LTO
builds on Mac and PS4

Differential revision: https://reviews.llvm.org/D68950
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/lib/Driver/ToolChains/Clang.cppclang.src/lib/Driver/ToolChains/Clang.cpp
The file was modified/cfe/trunk/test/Driver/lto-unit.cclang.src/test/Driver/lto-unit.c
Revision 375222 by huntergr:
[AArch64][SVE] Add SPLAT_VECTOR ISD Node

Adds a new ISD node to replicate a scalar value across all elements of
a vector. This is needed for scalable vectors, since BUILD_VECTOR cannot
be used.

Fixes up default type legalization for scalable vectors after the
new MVT type ranges were introduced.

At present I only use this node for scalable vectors. A DAGCombine has
been added to transform a BUILD_VECTOR into a SPLAT_VECTOR if all
elements are the same, but only if the default operation action of
Expand has been overridden by the target.

I've only added result promotion legalization for scalable vector
i8/i16/i32/i64 types in AArch64 for now.

Reviewers: t.p.northover, javed.absar, greened, cameron.mcinally, jmolloy

Reviewed By: jmolloy

Differential Revision: https://reviews.llvm.org/D47775
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/ISDOpcodes.hllvm.src/include/llvm/CodeGen/ISDOpcodes.h
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cppllvm.src/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cppllvm.src/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cppllvm.src/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.hllvm.src/lib/CodeGen/SelectionDAG/LegalizeTypes.h
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cppllvm.src/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cppllvm.src/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
The file was modified/llvm/trunk/lib/CodeGen/TargetLoweringBase.cppllvm.src/lib/CodeGen/TargetLoweringBase.cpp
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cppllvm.src/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.hllvm.src/lib/Target/AArch64/AArch64ISelLowering.h
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.tdllvm.src/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modified/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.tdllvm.src/lib/Target/AArch64/SVEInstrFormats.td
The file was added/llvm/trunk/test/CodeGen/AArch64/sve-vector-splat.llllvm.src/test/CodeGen/AArch64/sve-vector-splat.ll
Revision 375220 by sjoerdmeijer:
[Arm][libsanitizer] Fix arm libsanitizer failure with bleeding edge glibc

Glibc has recently introduced changed to the mode field in ipc_perm in commit
2f959dfe849e0646e27403f2e4091536496ac0f0. For Arm this means that the mode
field no longer has the same size.

This causes an assert failure against libsanitizer's internal copy of ipc_perm.
Since this change can't be easily detected I am adding arm to the list of
targets that are excluded from this check.

Patch by: Tamar Christina

Differential Revision: https://reviews.llvm.org/D69104
Change TypePath in RepositoryPath in Workspace
The file was modified/compiler-rt/trunk/lib/sanitizer_common/sanitizer_platform_limits_posix.cppcompiler-rt.src/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp
Revision 375219 by evgeny777:
[ThinLTOCodeGenerator] Add support for index-based WPD

Differential revision: https://reviews.llvm.org/D68950
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/LTO/ThinLTOCodeGenerator.cppllvm.src/lib/LTO/ThinLTOCodeGenerator.cpp
The file was added/llvm/trunk/test/ThinLTO/X86/devirt_promote_legacy.llllvm.src/test/ThinLTO/X86/devirt_promote_legacy.ll
Revision 375217 by dmgreen:
[AArch64] Don't combine callee-save and local stack adjustment when optimizing for size

For arm64, D18619 introduced the ability to combine bumping the stack pointer
upfront in case it needs to be bumped for both the callee-save area as well as
the local stack area.

That diff already remarks that "This change can cause an increase in
instructions", but argues that even when that happens, it should be still be a
performance benefit because the number of micro-ops is reduced.

We have observed that this code-size increase can be significant in practice.
This diff disables combining stack bumping for methods that are marked as
optimize-for-size.

Example of a prologue with the behavior before this diff (combining stack bumping when possible):
  sub        sp, sp, #0x40
  stp        d9, d8, [sp, #0x10]
  stp        x20, x19, [sp, #0x20]
  stp        x29, x30, [sp, #0x30]
  add        x29, sp, #0x30
  [... compute x8 somehow ...]
  stp        x0, x8, [sp]

And after this  diff, if the method is marked as optimize-for-size:
  stp        d9, d8, [sp, #-0x30]!
  stp        x20, x19, [sp, #0x10]
  stp        x29, x30, [sp, #0x20]
  add        x29, sp, #0x20
  [... compute x8 somehow ...]
  stp        x0, x8, [sp, #-0x10]!

Note that without combining the stack bump there are two auto-decrements,
nicely folded into the stp instructions, whereas otherwise there is a single
sub sp, ... instruction, but not folded.

Patch by Nikolai Tillmann!

Differential Revision: https://reviews.llvm.org/D68530
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cppllvm.src/lib/Target/AArch64/AArch64FrameLowering.cpp
The file was added/llvm/trunk/test/CodeGen/AArch64/arm64-never-combine-csr-local-stack-bump-for-size.llllvm.src/test/CodeGen/AArch64/arm64-never-combine-csr-local-stack-bump-for-size.ll
Revision 375215 by rksimon:
[X86] Regenerate memcmp tests and add X64-AVX512 common prefix

Should help make the changes in D69157 clearer
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/memcmp.llllvm.src/test/CodeGen/X86/memcmp.ll
Revision 375214 by rksimon:
Fix MSVC "not all control paths return a value" warning. NFCI.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/tools/llvm-objcopy/CopyConfig.cppllvm.src/tools/llvm-objcopy/CopyConfig.cpp
Revision 375213 by rksimon:
Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warnings. NFCI.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Object/MachOUniversal.cppllvm.src/lib/Object/MachOUniversal.cpp
The file was modified/llvm/trunk/tools/llvm-objdump/MachODump.cppllvm.src/tools/llvm-objdump/MachODump.cpp
Revision 375212 by russell_gallop:
Remove -DLLVM_USE_LINKER from Windows self host bots.

LLVM_USE_LINKER sets the -fuse-ld. This is redundant as the linker is set to
lld-link.

Differential Revision: https://reviews.llvm.org/D69098
Change TypePath in RepositoryPath in Workspace
The file was modified/zorg/trunk/zorg/buildbot/builders/annotated/clang-windows.pyzorg/zorg/buildbot/builders/annotated/clang-windows.py
The file was modified/zorg/trunk/zorg/buildbot/builders/annotated/sanitizer-windows.pyzorg/zorg/buildbot/builders/annotated/sanitizer-windows.py
Revision 375211 by dmgreen:
[Codegen] Alter the default promotion for saturating adds and subs

The default promotion for the add_sat/sub_sat nodes currently does:
    ANY_EXTEND iN to iM
    SHL by M-N
    [US][ADD|SUB]SAT
    L/ASHR by M-N

If the promoted add_sat or sub_sat node is not legal, this can produce code
that effectively does a lot of shifting (and requiring large constants to be
materialised) just to use the overflow flag. It is simpler to just do the
saturation manually, using the higher bitwidth addition and a min/max against
the saturating bounds. That is what this patch attempts to do.

Differential Revision: https://reviews.llvm.org/D68926
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cppllvm.src/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
The file was modified/llvm/trunk/test/CodeGen/AArch64/sadd_sat.llllvm.src/test/CodeGen/AArch64/sadd_sat.ll
The file was modified/llvm/trunk/test/CodeGen/AArch64/sadd_sat_plus.llllvm.src/test/CodeGen/AArch64/sadd_sat_plus.ll
The file was modified/llvm/trunk/test/CodeGen/AArch64/sadd_sat_vec.llllvm.src/test/CodeGen/AArch64/sadd_sat_vec.ll
The file was modified/llvm/trunk/test/CodeGen/AArch64/ssub_sat.llllvm.src/test/CodeGen/AArch64/ssub_sat.ll
The file was modified/llvm/trunk/test/CodeGen/AArch64/ssub_sat_plus.llllvm.src/test/CodeGen/AArch64/ssub_sat_plus.ll
The file was modified/llvm/trunk/test/CodeGen/AArch64/ssub_sat_vec.llllvm.src/test/CodeGen/AArch64/ssub_sat_vec.ll
The file was modified/llvm/trunk/test/CodeGen/AArch64/uadd_sat.llllvm.src/test/CodeGen/AArch64/uadd_sat.ll
The file was modified/llvm/trunk/test/CodeGen/AArch64/uadd_sat_plus.llllvm.src/test/CodeGen/AArch64/uadd_sat_plus.ll
The file was modified/llvm/trunk/test/CodeGen/AArch64/uadd_sat_vec.llllvm.src/test/CodeGen/AArch64/uadd_sat_vec.ll
The file was modified/llvm/trunk/test/CodeGen/AArch64/usub_sat.llllvm.src/test/CodeGen/AArch64/usub_sat.ll
The file was modified/llvm/trunk/test/CodeGen/AArch64/usub_sat_plus.llllvm.src/test/CodeGen/AArch64/usub_sat_plus.ll
The file was modified/llvm/trunk/test/CodeGen/AArch64/usub_sat_vec.llllvm.src/test/CodeGen/AArch64/usub_sat_vec.ll
The file was modified/llvm/trunk/test/CodeGen/ARM/sadd_sat.llllvm.src/test/CodeGen/ARM/sadd_sat.ll
The file was modified/llvm/trunk/test/CodeGen/ARM/sadd_sat_plus.llllvm.src/test/CodeGen/ARM/sadd_sat_plus.ll
The file was modified/llvm/trunk/test/CodeGen/ARM/ssub_sat.llllvm.src/test/CodeGen/ARM/ssub_sat.ll
The file was modified/llvm/trunk/test/CodeGen/ARM/ssub_sat_plus.llllvm.src/test/CodeGen/ARM/ssub_sat_plus.ll
The file was modified/llvm/trunk/test/CodeGen/ARM/uadd_sat.llllvm.src/test/CodeGen/ARM/uadd_sat.ll
The file was modified/llvm/trunk/test/CodeGen/ARM/uadd_sat_plus.llllvm.src/test/CodeGen/ARM/uadd_sat_plus.ll
The file was modified/llvm/trunk/test/CodeGen/ARM/usub_sat.llllvm.src/test/CodeGen/ARM/usub_sat.ll
The file was modified/llvm/trunk/test/CodeGen/ARM/usub_sat_plus.llllvm.src/test/CodeGen/ARM/usub_sat_plus.ll
The file was modified/llvm/trunk/test/CodeGen/X86/sadd_sat.llllvm.src/test/CodeGen/X86/sadd_sat.ll
The file was modified/llvm/trunk/test/CodeGen/X86/sadd_sat_plus.llllvm.src/test/CodeGen/X86/sadd_sat_plus.ll
The file was modified/llvm/trunk/test/CodeGen/X86/ssub_sat.llllvm.src/test/CodeGen/X86/ssub_sat.ll
The file was modified/llvm/trunk/test/CodeGen/X86/ssub_sat_plus.llllvm.src/test/CodeGen/X86/ssub_sat_plus.ll
The file was modified/llvm/trunk/test/CodeGen/X86/uadd_sat.llllvm.src/test/CodeGen/X86/uadd_sat.ll
The file was modified/llvm/trunk/test/CodeGen/X86/uadd_sat_plus.llllvm.src/test/CodeGen/X86/uadd_sat_plus.ll
The file was modified/llvm/trunk/test/CodeGen/X86/usub_sat.llllvm.src/test/CodeGen/X86/usub_sat.ll
The file was modified/llvm/trunk/test/CodeGen/X86/usub_sat_plus.llllvm.src/test/CodeGen/X86/usub_sat_plus.ll
Revision 375210 by kmclaughlin:
[AArch64][SVE] Implement unpack intrinsics

Summary:
Implements the following intrinsics:
  - int_aarch64_sve_sunpkhi
  - int_aarch64_sve_sunpklo
  - int_aarch64_sve_uunpkhi
  - int_aarch64_sve_uunpklo

This patch also adds AArch64ISD nodes for UNPK instead of implementing
the intrinsics directly, as they are required for a future patch which
implements the sign/zero extension of legal vectors.

This patch includes tests for the Subdivide2Argument type added by D67549

Reviewers: sdesmalen, SjoerdMeijer, greened, rengolin, rovka

Reviewed By: greened

Subscribers: tschuett, kristof.beyls, rkruppe, psnobl, cfe-commits, llvm-commits

Differential Revision: https://reviews.llvm.org/D67550
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/IR/IntrinsicsAArch64.tdllvm.src/include/llvm/IR/IntrinsicsAArch64.td
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cppllvm.src/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.hllvm.src/lib/Target/AArch64/AArch64ISelLowering.h
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.tdllvm.src/lib/Target/AArch64/AArch64InstrInfo.td
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.tdllvm.src/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modified/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.tdllvm.src/lib/Target/AArch64/SVEInstrFormats.td
The file was added/llvm/trunk/test/CodeGen/AArch64/sve-intrinsics-perm-select.llllvm.src/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll