FailedChanges

Changes from Git (git http://labmaster3.local/git/llvm-zorg.git)

Summary

  1. Added support for git/github to OpenMPBuilder. (details)
Commit d755ff9ed86f716253c2b6566e52b1801ff7201c by gkistanova
Added support for git/github to OpenMPBuilder.
The file was modifiedzorg/buildbot/builders/OpenMPBuilder.py

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. Revert "Use -fdebug-compilation-dir to form absolute paths in coverage (details)
  2. [MachineOutliner][NFC] clang-formating the MachineOutliner. (details)
  3. Revert "[Concepts] Constraint Enforcement & Diagnostics" (details)
  4. [Docs] Repurpose 'sources' page as 'contributing'. (details)
  5. [NFCI][XCOFF][AIX] Skip empty Section during object file generation (details)
  6. [scudo][standalone] Lists fix (details)
  7. Revert "[clang] Add no_builtin attribute" (details)
  8. [PowerPC] Do not emit HW loop if the body contains calls to lrint/lround (details)
  9. [Builtins] Teach Clang about memccpy (details)
  10. [debugserver] Detect arch from LLVM_DEFAULT_TARGET_TRIPLE (details)
  11. [AArch64][GlobalISel] Fix assertion fail in C++ selection for vector (details)
  12. Modernize TestThreadStepOut.py (details)
  13. [lldb] move package generation from python to cmake (details)
  14. Recommit "Add a heap alloc site marker field to the ExtraInfo in (details)
  15. Replace abort with llvm_unreachable. (details)
  16. [NFC] Fix some indentation disturbed in D67368 (details)
  17. [PowerPC] Emit scalar fp min/max instructions (details)
  18. [clang][clang-scan-deps] Add -fcxx-modules to test for Darwin. (details)
  19. gn build: (manually) merge 75f72f6b (details)
  20. [msan] Remove more attributes from sanitized functions. (details)
  21. gn build: fix bad merge of 75f72f6b done in 3431f1ba (details)
  22. PR43764: Qualify a couple of calls to forward_as_tuple to be (details)
  23. gn build: Merge 38839d08b8e (details)
  24. [Attributor] Make IntegerState more flexible (details)
  25. Fix a few typos in lld/ELF to cycle bots (details)
  26. [lit] Remove callback indirection (details)
  27. [RISCV] Remove RA from reserved register to use as callee saved register (details)
  28. AMDGPU: Make VReg_1 only include 1 artificial register (details)
  29. [JITLink] Tighten section sorting criteria to fix a flaky test case. (details)
Commit 7cd595df96d5929488063d8ff5cc3b5d800386da by rnk
Revert "Use -fdebug-compilation-dir to form absolute paths in coverage
mappings"
This reverts commit 9d4806a387892972fd544c0dcaefb0926126220c.
There seem to be bugs in llvm-cov --path-equivalence that are causing
Chromium problems. Revert this until they are understood or fixed.
The file was removedclang/test/CoverageMapping/debug-dir.cpp
The file was modifiedclang/lib/CodeGen/CoverageMappingGen.cpp
The file was modifiedclang/lib/CodeGen/CoverageMappingGen.h
Commit 6b7615ae9a2296f7190b126d7573bfa3310d8afc by puyan
[MachineOutliner][NFC] clang-formating the MachineOutliner.
The file was modifiedllvm/lib/CodeGen/MachineOutliner.cpp
Commit 38839d08b8e165dfaab0fa6acc77e620d6df294c by vtsyrklevich
Revert "[Concepts] Constraint Enforcement & Diagnostics"
This reverts commit ffa214ef22892d75340dc6720271863901dc2c90, it was
causing ASAN test failures on sanitizer-x86_64-linux-bootstrap.
The file was removedclang/include/clang/AST/ASTConcept.h
The file was modifiedclang/include/clang/AST/ExprCXX.h
The file was modifiedclang/lib/AST/CMakeLists.txt
The file was modifiedclang/lib/Sema/SemaTemplate.cpp
The file was modifiedclang/lib/Serialization/ASTReaderStmt.cpp
The file was modifiedclang/lib/AST/ExprCXX.cpp
The file was modifiedclang/lib/Sema/SemaTemplateInstantiateDecl.cpp
The file was modifiedclang/include/clang/Sema/Sema.h
The file was removedclang/test/CXX/temp/temp.constr/temp.constr.constr/non-function-templates.cpp
The file was modifiedclang/include/clang/Sema/TemplateDeduction.h
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/lib/Sema/SemaOverload.cpp
The file was modifiedclang/lib/Sema/SemaTemplateDeduction.cpp
The file was removedclang/test/CXX/temp/temp.constr/temp.constr.constr/partial-specializations.cpp
The file was modifiedclang/lib/Sema/SemaDeclCXX.cpp
The file was modifiedclang/lib/AST/Decl.cpp
The file was modifiedclang/test/CXX/expr/expr.prim/expr.prim.id/p3.cpp
The file was removedclang/lib/AST/ASTConcept.cpp
The file was modifiedclang/lib/Sema/SemaTemplateInstantiate.cpp
The file was removedclang/test/CXX/temp/temp.constr/temp.constr.constr/function-templates.cpp
The file was modifiedclang/lib/AST/ASTContext.cpp
The file was modifiedclang/lib/Sema/SemaConcept.cpp
The file was modifiedclang/lib/Serialization/ASTWriterStmt.cpp
Commit 5ae881f96f999aaca98d8f83d3f00e037c783647 by Jonas Devlieghere
[Docs] Repurpose 'sources' page as 'contributing'.
The page describing how to get the sources was more about contributing
to LLDB than getting the actual source. This patch moves some things
around and repurposes this page as a contributing to LLDB landing page.
The file was removedlldb/docs/resources/source.rst
The file was modifiedlldb/docs/resources/build.rst
The file was addedlldb/docs/resources/contributing.rst
The file was modifiedlldb/docs/index.rst
The file was modifiedlldb/docs/.htaccess
Commit d83a2faacd3bce3885bb9574ec4169c9c8943144 by jasonliu
[NFCI][XCOFF][AIX] Skip empty Section during object file generation
This is a fix to D69112 where we common up the logic of writing
CsectGroup. However, we forget to skip the Sections that are empty in
that patch.
Reviewed by: daltenty, xingxue
Differential Revision: https://reviews.llvm.org/D69447
The file was modifiedllvm/lib/MC/XCOFFObjectWriter.cpp
Commit 2513250be336ad92af47da2c225e7b7b69b9922f by 31459023+hctim
[scudo][standalone] Lists fix
Summary: Apparently during the review of D69265, and my flailing around
with git, a somewhat important line disappeared.
On top of that, there was no test exercising that code path, and while
writing the follow up patch I intended to write, some `CHECK`s were
failing.
Re-add the missing line, and add a test that fails without said line.
Reviewers: hctim, morehouse, pcc, cferris
Reviewed By: hctim
Subscribers: #sanitizers, llvm-commits
Tags: #sanitizers, #llvm
Differential Revision: https://reviews.llvm.org/D69529
The file was modifiedcompiler-rt/lib/scudo/standalone/list.h
The file was modifiedcompiler-rt/lib/scudo/standalone/tests/list_test.cpp
Commit ad531fff81a2a266ffed1d7da3333778cb59c983 by vtsyrklevich
Revert "[clang] Add no_builtin attribute"
This reverts commit bd87916109483d33455cbf20da2309197b983cdd. It was
causing ASan/MSan failures on the sanitizer buildbots.
The file was modifiedclang/include/clang/AST/Decl.h
The file was modifiedclang/lib/CodeGen/CGCall.cpp
The file was modifiedclang/include/clang/Basic/AttrDocs.td
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was modifiedclang/test/Misc/pragma-attribute-supported-attributes-list.test
The file was removedclang/test/Sema/no-builtin.cpp
The file was removedclang/test/CodeGen/no-builtin.cpp
The file was modifiedclang/lib/Sema/SemaDeclAttr.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/include/clang/Basic/Attr.td
Commit 97e36260709c541044f30092b420238511e13e5b by nemanjai
[PowerPC] Do not emit HW loop if the body contains calls to lrint/lround
These two intrinsics are lowered to calls so should prevent the
formation of CTR loops. In a subsequent patch, we will handle all
currently known intrinsics and prevent the formation of HW loops if any
unknown intrinsics are encountered.
Differential revision: https://reviews.llvm.org/D68841
The file was modifiedllvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
The file was addedllvm/test/CodeGen/PowerPC/pr43527.ll
Commit dfece0a108a71b493bb92f135f68c59fd1d85c06 by Dávid Bolvanský
[Builtins] Teach Clang about memccpy
Summary: Hopefully, -fno-builtin-memccpy will work now. Required for
https://reviews.llvm.org/D67986.
Reviewers: aaron.ballman, rsmith
Reviewed By: aaron.ballman
Subscribers: RKSimon, kristina, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D68377
The file was addedclang/test/CodeGen/memccpy-libcall.c
The file was modifiedclang/include/clang/Basic/Builtins.def
The file was modifiedclang/test/CodeGen/builtin-memfns.c
Commit 82d3ba87d06f9e2abc6e27d8799587d433c56630 by Vedant Kumar
[debugserver] Detect arch from LLVM_DEFAULT_TARGET_TRIPLE
The debugserver build needs to conditionally include files depending on
the target architecture.
Switch on the architecture specified by LLVM_DEFAULT_TARGET_TRIPLE, as
the llvm and swift build systems use this variable to identify the
target (the latter, indirectly, through LLVM_HOST_TRIPLE).
It would be possible to switch on CMAKE_OSX_ARCHITECTURES, but the swift
build does not provide it, preferring instead to pass arch-specific
CFLAGS etc explicitly. Switching on LLVM_HOST_TRIPLE is also an option,
but it breaks down when cross-compiling.
Differential Revision: https://reviews.llvm.org/D69523
The file was modifiedlldb/tools/debugserver/source/MacOSX/CMakeLists.txt
Commit 0f6ed432d58e47e7082bfd44d7b29f3ee54e2642 by aemerson
[AArch64][GlobalISel] Fix assertion fail in C++ selection for vector
zext of <4 x s8>
We bailed out of dealing with vectors only after the assertion, move it
before.
Fixes PR43794
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
Commit 651b5e725ee6812fdabb369ed2ecd4740106a82c by jingham
Modernize TestThreadStepOut.py
This test was timing out on the swift CI bots.  I didn't see any obvious
reason for that, and the test hasn't had problems on greendragon.  OTOH,
it was a bit oddly written, and needed modernizing, so I did that.
Differential Revision: https://reviews.llvm.org/D69453
The file was modifiedlldb/packages/Python/lldbsuite/test/functionalities/thread/step_out/TestThreadStepOut.py
The file was modifiedlldb/packages/Python/lldbsuite/test/lldbutil.py
Commit 99046b873f7fbbd496fc7287dacfda737ef6b162 by hhb
[lldb] move package generation from python to cmake
Summary: This is the last part. And we can remove the python script.
Subscribers: lldb-commits, mgorny
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D69019
The file was removedlldb/scripts/Python/finishSwigPythonLLDB.py
The file was removedlldb/scripts/finishSwigWrapperClasses.py
The file was addedlldb/scripts/Python/createPythonInit.py
The file was modifiedlldb/CMakeLists.txt
The file was removedlldb/scripts/utilsArgsParse.py
The file was removedlldb/scripts/utilsOsType.py
The file was removedlldb/scripts/utilsDebug.py
Commit 742043047c973999eac7734e53f7872973933f24 by akhuang
Recommit "Add a heap alloc site marker field to the ExtraInfo in
MachineInstrs"
Summary: Fixes some things from original commit at
https://reviews.llvm.org/D69136. The main change is that the heap alloc
marker is always stored as ExtraInfo in the machine instruction instead
of in the PointerSumType because it cannot hold more than 4 pointer
types.
Add instruction marker to MachineInstr ExtraInfo. This does almost the
same thing as Pre/PostInstrSymbols, except that it doesn't create a
label until printing instructions. This allows for labels to be put
around instructions that are deleted/duplicated somewhere. Use this
marker to track heap alloc site call instructions.
Reviewers: rnk
Subscribers: MatzeB, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69536
The file was modifiedllvm/lib/CodeGen/AsmPrinter/CodeViewDebug.h
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
The file was modifiedllvm/include/llvm/CodeGen/MachineInstr.h
The file was modifiedllvm/lib/CodeGen/MachineFunction.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/FastISel.cpp
The file was modifiedllvm/test/CodeGen/X86/taildup-heapallocsite.ll
The file was modifiedllvm/lib/CodeGen/MachineInstr.cpp
The file was modifiedllvm/include/llvm/CodeGen/MachineFunction.h
The file was modifiedllvm/test/CodeGen/X86/label-heapallocsite.ll
The file was modifiedllvm/unittests/CodeGen/MachineInstrTest.cpp
Commit 01f3a59fb3e2542fce74c768718f594d0debd0da by joerg
Replace abort with llvm_unreachable.
The former depended on header pollution to be found and doesn't fit the
LLVM style of error handling.
The file was modifiedllvm/include/llvm/ADT/Hashing.h
Commit 9ecd3225d134541bdfde18a6648edb8b9e048035 by rnk
[NFC] Fix some indentation disturbed in D67368
The file was modifiedclang/lib/Sema/SemaType.cpp
The file was modifiedclang/include/clang/AST/Attr.h
Commit 25a41ad242000520629a274e83db1ea884d1c1e7 by nemanjai
[PowerPC] Emit scalar fp min/max instructions
VSX provides floating point minimum and maximum instructions that
conform to IEEE semantics. This legalizes the respective nodes and emits
VSX code for them. Furthermore, on Power9 cores we have xsmaxcdp and
xsmincdp instructions that conform to language semantics for the
conditional operator even in the presence of NaNs.
Differential revision: https://reviews.llvm.org/D62993
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrVSX.td
The file was modifiedllvm/test/CodeGen/PowerPC/ctr-minmaxnum.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.h
The file was addedllvm/test/CodeGen/PowerPC/scalar-min-max.ll
Commit dddec1f1840b8a019c8c89dd1e7961cf39d845d3 by michael_spencer
[clang][clang-scan-deps] Add -fcxx-modules to test for Darwin.
The file was modifiedclang/test/ClangScanDeps/Inputs/modules_cdb.json
Commit 3431f1ba4cccf073c5e8774540b3cc3df49868ac by nicolasweber
gn build: (manually) merge 75f72f6b
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/Transforms/Utils/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
The file was addedllvm/utils/gn/secondary/llvm/unittests/Target/X86/BUILD.gn
Commit 03e882050f1a28024dfd9d88688f718734c0b319 by eugenis
[msan] Remove more attributes from sanitized functions.
Summary: MSan instrumentation adds stores and loads even to pure
readonly/writeonly functions. It is removing some of those attributes
from instrumented functions and call targets, but apparently not enough.
Remove writeonly, argmemonly and speculatable in addition to readonly /
readnone.
Reviewers: pcc, vitalybuka
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69541
The file was modifiedllvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
The file was addedllvm/test/Instrumentation/MemorySanitizer/attributes.ll
Commit 8530f294f59a36e2188e2198275490e1d6616e7f by nicolasweber
gn build: fix bad merge of 75f72f6b done in 3431f1ba
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/Transforms/Utils/BUILD.gn
Commit e658b3eb9728eb33154233ce09fca39f89d71840 by dblaikie
PR43764: Qualify a couple of calls to forward_as_tuple to be
ADL-resilient.
The file was modifiedlibcxx/include/tuple
The file was modifiedlibcxx/test/std/utilities/tuple/tuple.tuple/tuple.creation/tuple_cat.pass.cpp
Commit 8a3a5f93b2aa3c0983f100cabd82d0edb6373cae by llvmgnsyncbot
gn build: Merge 38839d08b8e
The file was modifiedllvm/utils/gn/secondary/clang/lib/AST/BUILD.gn
Commit 1a74645a70b38b48ff93251f7e7e51b2ab2ab403 by johannes
[Attributor] Make IntegerState more flexible
To make IntegerState more flexible but also less error prone we split it
up into (1) incrementing, (2) decrementing, and (3) bit-tracking states.
This adds functionality compared to before and disallows misuse, e.g.,
"incrementing" updates on a bit-tracking state.
Part of the change is a single operator in the base class which
simplifies helper functions that deal with states.
There are certain functional changes but all of which should actually be
corrections.
The file was modifiedllvm/include/llvm/Transforms/IPO/Attributor.h
The file was modifiedllvm/lib/Transforms/IPO/Attributor.cpp
Commit 5976a3f5aa990208326c0409e053ed85fdb74e2c by nicolasweber
Fix a few typos in lld/ELF to cycle bots
The file was modifiedlld/ELF/SymbolTable.cpp
The file was modifiedlld/ELF/MarkLive.cpp
The file was modifiedlld/ELF/SyntheticSections.cpp
The file was modifiedlld/ELF/Writer.cpp
The file was modifiedlld/ELF/LinkerScript.h
The file was modifiedlld/ELF/ARMErrataFix.cpp
The file was modifiedlld/ELF/Driver.cpp
The file was modifiedlld/ELF/Thunks.cpp
The file was modifiedlld/ELF/OutputSections.cpp
The file was modifiedlld/ELF/Symbols.h
The file was modifiedlld/ELF/CallGraphSort.cpp
The file was modifiedlld/ELF/InputSection.cpp
The file was modifiedlld/ELF/Relocations.cpp
The file was modifiedlld/ELF/Arch/PPC64.cpp
The file was modifiedlld/ELF/SyntheticSections.h
The file was modifiedlld/ELF/AArch64ErrataFix.cpp
The file was modifiedlld/ELF/Options.td
The file was modifiedlld/ELF/Config.h
The file was modifiedlld/ELF/InputFiles.cpp
Commit 7cd301677461b16a1a5a437a6f6be0b5f0125eaf by julian.lettner
[lit] Remove callback indirection
The callback provides no benefits since `run.execute()` does not take
any arguments anymore.
The file was modifiedllvm/utils/lit/lit/main.py
Commit c1498e37abe6ff1f3e338551c1d94d294a7e5ac4 by shiva0217
[RISCV] Remove RA from reserved register to use as callee saved register
Remove RA from reserved register list, so we could use it as callee
saved register
Differential Revision: https://reviews.llvm.org/D67698
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
The file was modifiedllvm/test/CodeGen/RISCV/callee-saved-gprs.ll
Commit 21bc8e5a137d76879223ac2d8ff1ba92e2ea3acb by arsenm2
AMDGPU: Make VReg_1 only include 1 artificial register
When TableGen is inferring register classes from contexts, it uses a
sorting function based on the number of registers in the class. Since
this was being treated as an alias of VGPR_32, they had exactly the same
size. The sort used wasn't a stable sort, and even if it were, I believe
the tie breaker would effectively end up being the alphabetical ordering
of the class name. There appear to be issues trying to use an empty set
of registers, so add only one so this will always sort to the end.
Also add a comment explaining how VReg_1 is a dirty hack for
SelectionDAG.
This does end up changing the behavior of i1 with inline asm and VGPR
constraints, but the existing behavior was was already nonsensical and
inconsistent. It should probably be disallowed anyway.
Fixes bug 43699
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.td
The file was modifiedllvm/test/CodeGen/AMDGPU/inline-asm.ll
Commit 5a955cc8b95a88fd0489d9b0a36ec86941ba6337 by Lang Hames
[JITLink] Tighten section sorting criteria to fix a flaky test case.
Sections may have zero size and zero-sized sections may share a start
address with other zero-sized sections. For the section overlap test to
function correctly zero-sized sections must be ordered before any
non-zero sized ones.
This should fix the intermittent failures in the
test/ExecutionEngine/JITLink/X86/MachO_zero_fill_alignment.s test case
that have been observed on some builders.
The file was modifiedllvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.cpp