FailedChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. DAG: Add DAG argument to isFPExtFoldable (details)
  2. [utils] Reflow asm check generation to tolerate blank lines (details)
  3. [X86] Reland: Enable YMM memcmp with AVX1 (details)
  4. AMDGPU: Add default denormal mode to MachineFunctionInfo (details)
  5. [compiler-rt] [profile] Fix building for MinGW after d889d1efefe9f (details)
  6. [GlobalISel] Match table opt: fix a bug in matching num of operands (details)
Commit 622176705550d5af5e2837f4b2188ce9f7590887 by arsenm2
DAG: Add DAG argument to isFPExtFoldable
For AMDGPU this is dependent on the FP mode, which should eventually not
be a property of the subtarget.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.h
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
Commit a8a89c77ea3c16b45763fca6940bbfd3bef7884f by simon
[utils] Reflow asm check generation to tolerate blank lines
This change introduces two fixes. The second fix allows to generate a
test to check the first fix.
- Output `CHECK-EMPTY` prefix for an empty line in ASM output. Before
that
fix `update_llc_test_checks.py` incorrectly emits `CHECK-NEXT: <space>`
prefix.
- Fix the `ASM_FUNCTION_MIPS_RE` regex to stop on a real function
epilogue not on an inline assembler prologue and include inline
assembler code into a test.
Differential Revision: https://reviews.llvm.org/D47192
The file was modifiedllvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll
The file was modifiedllvm/utils/UpdateTestChecks/asm.py
The file was modifiedllvm/utils/UpdateTestChecks/common.py
Commit cb6822c9deb63b6c21263b3732e549fdc89c4bbf by dave
[X86] Reland: Enable YMM memcmp with AVX1
Update TargetTransformInfo to allow AVX1 to use YMM registers for
memcmp.
This is a follow up to D68632 which enabled XOR compares which made this
possible.
This also updates the memcmp-optsize.ll test unlike the first patch.
https://reviews.llvm.org/D69658
The file was modifiedllvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/CodeGen/X86/memcmp.ll
The file was modifiedllvm/test/CodeGen/X86/memcmp-optsize.ll
Commit 19e7f8a21d62d0a6ae8a1bbecb232bd9d520555b by arsenm2
AMDGPU: Add default denormal mode to MachineFunctionInfo
The default FP mode should really be a property of a specific function,
and not a subtarget. Introduce the necessary fields to the
SIMachineFunctionInfo to help move towards this goal.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
The file was modifiedllvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
The file was modifiedllvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
Commit ec630194fe64e9e304487040e808d0696a4f1895 by martin
[compiler-rt] [profile] Fix building for MinGW after d889d1efefe9f
This commit added use of a Windows API in InstrProfilingPort.h. When
_MSC_VER is defined (for MSVC), windows.h is already included earlier in
the same header (for atomics), but MinGW, the gcc atomics builtins are
used instead. Therefore explicitly include windows.h here, where the API
is used.
The file was modifiedcompiler-rt/lib/profile/InstrProfilingPort.h
Commit 6082a062a76d0bc9c9c641f5600569bafdf4c338 by rtereshin
[GlobalISel] Match table opt: fix a bug in matching num of operands
If there is a dag node with a variable number of operands that has at
least N operands (for some non-negative N), and multiple patterns with
that node with different number of operands, we would drop the number of
operands check in patterns with N operands, presumably because it's
guaranteed in such case that none of the per-operand checks will access
the operand list out-of-bounds.
Except semantically the check is about having exactly N operands, not at
least N operands, and a backend might rely on it to disambiguate
different patterns.
In this patch we change the condition on emitting the number of operands
check from "the instruction is not guaranteed to have at least as many
operands as are checked by the pattern being matched" to "the
instruction is not guaranteed to have a specific number of operands".
We're relying (still) on the rest of the CodeGenPatterns mechanics to
validate that the pattern itself doesn't try to access more operands
than there is in the instruction in cases when the instruction does have
fixed number of operands, and on the machine verifier to validate at
runtime that particular MIs like that satisfy the constraint as well.
Reviewers: dsanders, qcolombet
Reviewed By: qcolombet
Subscribers: arsenm, rovka, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69653
The file was addedllvm/test/TableGen/GlobalISelEmitterVariadic.td
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp