FailedChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [IR] Add Freeze instruction (details)
  2. [X86] Lower the cost of avx512 horizontal bool and/or reductions to (details)
  3. [IR] Remove switch's default block that causes clang 8 raise error (details)
  4. [lldb][NFC] Give some parameters in CommandInterpreter more descriptive (details)
  5. [AArch64] Update test checks on merge-store-dependency.ll. NFC (details)
  6. Recommit "[HardwareLoops] Optimisation remarks" (details)
  7. [mips] Fix `__mips_isa_rev` macros value for Octeon CPU (details)
  8. [mips] Set __OCTEON__ macros (details)
  9. DWARFDebugLoclists: Make it possible to read relocated addresses (details)
  10. [RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hook (details)
  11. [InstCombine] dropRedundantMaskingOfLeftShiftInput(): truncation (details)
  12. [LoopUnroll] peel-loop-conditions.ll: add some 'is even/odd' peeling (details)
  13. MemoryRegion: Print "don't know" permission values as such (details)
  14. lldb/minidump: Add support for the alternate ARM64 constant (details)
  15. [OpenCL] Add builtin function attribute handling (details)
  16. [OpenCL] Group builtin functions by prototype (details)
  17. Revert and patch "[Python] Remove readline module" (details)
  18. lldb/breakpad: add suppport for the "x86_64h" architecture (details)
  19. [Scheduling][ARM] Consistently enable PostRA Machine scheduling (details)
Commit 58acbce3def63a207b8f5a69318a99666a4aac53 by aqjune
[IR] Add Freeze instruction
Summary:
- Define Instruction::Freeze, let it be UnaryOperator
- Add support for freeze to LLLexer/LLParser/BitcodeReader/BitcodeWriter
The format is `%x = freeze <ty> %v`
- Add support for freeze instruction to llvm-c interface.
- Add m_Freeze in PatternMatch.
- Erase freeze when lowering IR to SelDag.
Reviewers: deadalnix, hfinkel, efriedma, lebedev.ri, nlopes, jdoerfert,
regehr, filcab, delcypher, whitequark
Reviewed By: lebedev.ri, jdoerfert
Subscribers: jfb, kristof.beyls, hiraditya, lebedev.ri, steven_wu,
dexonsmith, xbolva00, delcypher, spatel, regehr, trentxintong, vsk,
filcab, nlopes, mehdi_amini, deadalnix, llvm-commits
Differential Revision: https://reviews.llvm.org/D29011
The file was modifiedllvm/lib/AsmParser/LLParser.cpp
The file was modifiedllvm/lib/IR/Instructions.cpp
The file was modifiedllvm/include/llvm/IR/Instruction.def
The file was modifiedllvm/include/llvm-c/Core.h
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
The file was modifiedllvm/lib/IR/Core.cpp
The file was modifiedllvm/include/llvm/IR/PatternMatch.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/include/llvm/IR/IRBuilder.h
The file was addedllvm/test/Bindings/llvm-c/freeze.ll
The file was modifiedllvm/lib/AsmParser/LLToken.h
The file was modifiedllvm/lib/Bitcode/Reader/BitcodeReader.cpp
The file was modifiedllvm/include/llvm/IR/Operator.h
The file was modifiedllvm/test/Bitcode/compatibility.ll
The file was modifiedllvm/test/Transforms/MergeFunc/inline-asm.ll
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was modifiedllvm/lib/IR/Instruction.cpp
The file was modifiedllvm/test/Bindings/OCaml/core.ml
The file was modifiedllvm/lib/Bitcode/Writer/BitcodeWriter.cpp
The file was modifiedllvm/lib/CodeGen/TargetLoweringBase.cpp
The file was modifiedllvm/include/llvm/Bitcode/LLVMBitCodes.h
The file was modifiedllvm/lib/IR/ConstantFold.cpp
The file was modifiedllvm/tools/llvm-c-test/echo.cpp
The file was modifiedllvm/lib/AsmParser/LLLexer.cpp
Commit 103968d147b135ebfcee69d6d7a1428163e66aaa by craig.topper
[X86] Lower the cost of avx512 horizontal bool and/or reductions to
2*log2(bitwidth)+1 for legal types.
This better represents the kshift+binop we'd get for each stage before
the final extract. Its likely we'll do even better by doing a kmov and a
cmp with a GPR, but this is a good start.
The default handling was costing a worst case single source permute
shuffle of the vector before the binop. This worst case assumes the
shuffle might have to be emulated with extracts and inserts. But since
we know we're doing a reduction we can assume we'll get kshift lowering.
There's still some room for improvement here, but this is much better
than it was.
The file was modifiedllvm/test/Analysis/CostModel/X86/reduce-or.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/X86/reduce-and.ll
Commit 92ef101da91d39525043034694b3088d0a08f43f by aqjune
[IR] Remove switch's default block that causes clang 8 raise error
The file was modifiedllvm/lib/IR/ConstantFold.cpp
Commit db5074dc10222a8202adcd7c1da1acd2828fbecb by Raphael Isemann
[lldb][NFC] Give some parameters in CommandInterpreter more descriptive
names
The file was modifiedlldb/source/Interpreter/CommandInterpreter.cpp
The file was modifiedlldb/include/lldb/Interpreter/CommandInterpreter.h
Commit edfb8eea575582f5a4f485368d84b7c5e9853780 by david.green
[AArch64] Update test checks on merge-store-dependency.ll. NFC
The file was modifiedllvm/test/CodeGen/AArch64/merge-store-dependency.ll
Commit 92164cf25d513d44fdb5d727a33d02ad4c87384e by sjoerd.meijer
Recommit "[HardwareLoops] Optimisation remarks"
With a few things fixed:
- initialisaiton of the optimisation remark pass (this was causing the
buildbot
failures on PPC),
- a test case.
Differential Revision: https://reviews.llvm.org/D69660
The file was modifiedllvm/test/Transforms/HardwareLoops/ARM/structure.ll
The file was modifiedllvm/test/CodeGen/ARM/O3-pipeline.ll
The file was modifiedllvm/lib/CodeGen/HardwareLoops.cpp
Commit e578d0fd295a67bce1e1fc922237f459deb49c7e by simon
[mips] Fix `__mips_isa_rev` macros value for Octeon CPU
The file was modifiedclang/lib/Basic/Targets/Mips.cpp
The file was modifiedclang/test/Preprocessor/init.c
Commit 0d14656b9d8ca38b8ea321c7047eaeec43c5b2ef by simon
[mips] Set __OCTEON__ macros
The file was modifiedclang/lib/Basic/Targets/Mips.cpp
The file was modifiedclang/test/Preprocessor/init.c
Commit b4c5b8f3f51206bac2282a8b483e76ad59a5aed5 by pavel
DWARFDebugLoclists: Make it possible to read relocated addresses
Summary: Handling relocations was not needed when the loclists section
was a DWO-only thing. But since DWARF5, it is possible to use it in
regular objects too, and the standard permits embedding addresses into
the section directly. These addresses need to be relocated in unlinked
files.
Reviewers: JDevlieghere, dblaikie, probinson
Subscribers: aprantl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68271
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFContext.cpp
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFDebugLoc.cpp
The file was modifiedllvm/include/llvm/DebugInfo/DWARF/DWARFDebugLoc.h
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFDie.cpp
The file was addedllvm/test/tools/llvm-dwarfdump/X86/debug_loclists.s
Commit 0d47c7aba364962d14e4e25249d75da7bdf29b78 by luismarques
[RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hook
Summary: Introduces the `InstrInfo::areMemAccessesTriviallyDisjoint`
hook. The test could check for instruction reorderings, but to avoid
being brittle it just checks instruction dependencies.
Reviewers: asb, lenary Reviewed By: lenary Tags: #llvm Differential
Revision: https://reviews.llvm.org/D67046
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.cpp
The file was addedllvm/test/CodeGen/RISCV/disjoint.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.h
Commit ccf1a5f4bbe680f20e26c29774d62bec6cb226da by lebedev.ri
[InstCombine] dropRedundantMaskingOfLeftShiftInput(): truncation
(PR42563)
Summary: That fold keeps growing and growing :( I think this may be one
of the last pieces for it.
Since D67677/D67725, the fold knowns the general form of the pattern -
where some masking is needed: https://rise4fun.com/Alive/F5R
https://rise4fun.com/Alive/gslRa
But there is one more huge piece missing - if you are extracting some
bits, it is not impossible that the origin is wider than the extraction,
i.e. there may be a truncation. And we don't deal with that yet.
But we can, and the generalization remains fully identical:
https://rise4fun.com/Alive/Uar https://rise4fun.com/Alive/5SW
After a preparatory cleanup i think the diff looks rather clean.
One missing piece is that in some patterns (especially pat. b),
`-1` only needs to be `-1` in final type, but that is for later..
https://bugs.llvm.org/show_bug.cgi?id=42563
Reviewers: spatel, nikic
Reviewed By: spatel
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69125
The file was modifiedllvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-c.ll
The file was modifiedllvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-c.ll
The file was modifiedllvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-e.ll
The file was modifiedllvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-d.ll
The file was modifiedllvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-f.ll
The file was modifiedllvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-a.ll
The file was modifiedllvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-d.ll
The file was modifiedllvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-a.ll
The file was modifiedllvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-b.ll
The file was modifiedllvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-b.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
The file was modifiedllvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-e.ll
Commit 12c4a71ca9dc19dc364cd6ad4cfc2a3787141c24 by lebedev.ri
[LoopUnroll] peel-loop-conditions.ll: add some 'is even/odd' peeling
tests
The file was modifiedllvm/test/Transforms/LoopUnroll/peel-loop-conditions.ll
Commit 28cf9698abd39221001ace885a7d1c1f488b967c by pavel
MemoryRegion: Print "don't know" permission values as such
Summary: The permissions in a memory region have ternary states (yes,
no, don't know), but the memory region command only prints in binary,
treating
"don't know" as "yes", which is particularly confusing as for instance
the unwinder will treat an unknown value as "no".
This patch makes is so that we distinguish all three states when
printing the values, using "?" to indicate the lack of information. It
is implemented via a special argument to the format provider for the
OptionalBool enumeration.
Reviewers: clayborg, jingham
Subscribers: lldb-commits
Differential Revision: https://reviews.llvm.org/D69106
The file was modifiedlldb/test/Shell/Minidump/memory-region-from-module.yaml
The file was modifiedlldb/source/Commands/CommandObjectMemory.cpp
The file was modifiedlldb/source/Target/MemoryRegionInfo.cpp
The file was modifiedlldb/include/lldb/Target/MemoryRegionInfo.h
Commit 4ecff91ed1df05edbdb55cb2ccdf58466f1333b0 by pavel
lldb/minidump: Add support for the alternate ARM64 constant
The file was modifiedlldb/source/Plugins/Process/minidump/MinidumpParser.cpp
The file was modifiedlldb/packages/Python/lldbsuite/test/functionalities/postmortem/minidump-new/regions-linux-map.yaml
Commit 9a8d477a0e00c15d6d33a52486fa931483b7f2ea by sven.vanhaastregt
[OpenCL] Add builtin function attribute handling
Add handling for the "pure", "const" and "convergent" function
attributes for OpenCL builtin functions.
Patch by Pierre Gondois and Sven van Haastregt.
Differential Revision: https://reviews.llvm.org/D64319
The file was modifiedclang/utils/TableGen/ClangOpenCLBuiltinEmitter.cpp
The file was addedclang/test/CodeGenOpenCL/fdeclare-opencl-builtins.cl
The file was modifiedclang/lib/Sema/SemaLookup.cpp
The file was modifiedclang/lib/Sema/OpenCLBuiltins.td
Commit 0e56b0f94bfc683c5a95e96784cfc9229a730bc8 by sven.vanhaastregt
[OpenCL] Group builtin functions by prototype
The TableGen-generated file containing the function definitions can be
reorganized to save some memory in the Clang binary.  Functions having
the same prototype(s) will point to a shared list of prototype(s).
Patch by Pierre Gondois and Sven van Haastregt.
Differential Revision: https://reviews.llvm.org/D63557
The file was modifiedclang/utils/TableGen/ClangOpenCLBuiltinEmitter.cpp
Commit 9357b5d08497326a1895cab6c1d712bf12a34519 by sguelton
Revert and patch "[Python] Remove readline module"
Fix https://bugs.llvm.org/show_bug.cgi?id=43830 while avoiding polluting
the global Python namespace.
This both reverts r357277 to rebundle a version of Python's readline
module based on libedit.
However, this patch also provides two improvements over the previous
implementation:
1. use PyMem_RawMalloc instead of PyMem_Malloc, as expected by
PyOS_Readline
  (prevents to segfault upon exit of interactive session) 2. patch the
readline module upon embedded interpreter loading, instead of
  patching it globally, which should prevent any side effect on other
  modules/packages 3. only activate the patched module if libedit is
actually linked in lldb
Differential Revision: https://reviews.llvm.org/D69793
The file was addedlldb/source/Plugins/ScriptInterpreter/Python/PythonReadline.h
The file was addedlldb/source/Plugins/ScriptInterpreter/Python/PythonReadline.cpp
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Python/CMakeLists.txt
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
Commit f71e35dc1f3ea9b368b1d4626ee9bf7993839084 by pavel
lldb/breakpad: add suppport for the "x86_64h" architecture
The file was modifiedlldb/test/Shell/SymbolFile/Breakpad/Inputs/line-table-edgecases.syms
The file was modifiedlldb/source/Plugins/ObjectFile/Breakpad/BreakpadRecords.cpp
Commit 7d9af03ff7a0d4fb6ae3ec224a0d8d7398bdbd84 by david.green
[Scheduling][ARM] Consistently enable PostRA Machine scheduling
In the ARM backend, for historical reasons we have only some targets
using Machine Scheduling. The rest use the old list scheduler as they
are using itinaries and the list scheduler seems to produce better code
(and not crash running out of register on v6m codes). So whether to use
the MIScheduler or not is checked at runtime from the subtarget
features.
This is fine, except for post-ra scheduling. Whether to use the old
post-ra list scheduler or the post-ra machine schedule is decided as the
pass manager is set up, in arms case from a newly constructed subtarget.
Under some situations, like LTO, this won't include the correct cpu so
can pick the wrong option. This can have a surprising effect on
performance.
To fix that, this patch overrides targetSchedulesPostRAScheduling and
addPreSched2 in the ARM backend, adding _both_ post-ra schedulers and
picking at runtime which to execute. To pick between the two I've had to
add a enablePostRAMachineScheduler() method that normally returns
enableMachineScheduler() && enablePostRAScheduler(), which can be
overridden to enable just one of PostRAMachineScheduler vs
PostRAScheduler.
Thanks to David Penry for the identifying this problem.
Differential Revision: https://reviews.llvm.org/D69775
The file was modifiedllvm/lib/Target/ARM/ARMSubtarget.h
The file was modifiedllvm/test/CodeGen/ARM/cortex-a57-misched-ldm.ll
The file was modifiedllvm/include/llvm/CodeGen/TargetSubtargetInfo.h
The file was modifiedllvm/test/CodeGen/ARM/cortex-a57-misched-stm.ll
The file was modifiedllvm/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll
The file was modifiedllvm/lib/CodeGen/MachineScheduler.cpp
The file was modifiedllvm/lib/Target/ARM/ARMSubtarget.cpp
The file was modifiedllvm/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll
The file was modifiedllvm/lib/CodeGen/TargetSubtargetInfo.cpp
The file was modifiedllvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll
The file was addedllvm/test/CodeGen/ARM/postrasched.ll
The file was modifiedllvm/test/CodeGen/ARM/cortex-a57-misched-vstm.ll
The file was modifiedllvm/lib/Target/ARM/ARMTargetMachine.h
The file was modifiedllvm/test/CodeGen/ARM/cortex-a57-misched-vldm.ll
The file was modifiedllvm/lib/Target/ARM/ARMTargetMachine.cpp
The file was modifiedllvm/test/CodeGen/ARM/O3-pipeline.ll
The file was modifiedllvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll