SuccessChanges

Summary

  1. AMDGPU: Move MnemonicAlias out of instruction def hierarchy Unfortunately MnemonicAlias defines a "Predicates" field just like an instruction or pattern, with a somewhat different interpretation. This ends up overriding the intended Predicates set by PredicateControl on the pseudoinstruction defintions with an empty list. This allowed incorrectly selecting instructions that should have been rejected due to the SubtargetPredicate from patterns on the instruction definition. This does remove the divergent predicate from the 64-bit shift patterns, which were already not used for the 32-bit shift, so I'm not sure what the point was. This also removes a second, redundant copy of the 64-bit divergent patterns.
  2. [SLP] add test for over-vectorization (PR33958); NFC
  3. [GlobalISel][AArch64] Handle tail calls with non-void return types Just return once you emit the call, which is exactly what SelectionDAG does in this situation. Update call-translator-tail-call.ll. Also update dllimport.ll to show that we tail call here in GISel again. Add -verify-machineinstrs to the GISel line too, to defend against verifier failures. Differential revision: https://reviews.llvm.org/D67282
  4. AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE Handle the simple case that lowers to a constant.
  5. AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR_TRUNC Treat this as legal on gfx9 since it can use S_PACK_* instructions for this. This isn't used by anything yet. The same will probably apply to 16-bit G_BUILD_VECTOR without the trunc.
  6. [clangd] Attempt to fix failing Windows buildbots. The assertion is failing on Windows, probably because path separator is different. For the failure see: http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast/builds/28072/steps/test/logs/stdio
  7. Revert "[MachineCopyPropagation] Remove redundant copies after TailDup via machine-cp" This reverts commit 371359. I'm suspecting a miscompile, I posted a reproducer to https://reviews.llvm.org/D65267.
  8. [yaml2obj] Simplify p_filesz/p_memsz computing This fixes a bug as well. When "FileSize:" (p_filesz) is specified and different from the actual value, the following code probably should not use PHeader.p_filesz: if (SHeader->sh_offset == PHeader.p_offset + PHeader.p_filesz) PHeader.p_memsz += SHeader->sh_size; Reviewed By: jhenderson Differential Revision: https://reviews.llvm.org/D67256
  9. [ARM] Fix loads and stores for predicate vectors These predicate vectors can usually be loaded and stored with a single instruction, a VSTR_P0. However this instruction will store the entire P0 predicate, 16 bits, zeroextended to 32bits. Each lane of the the v4i1/v8i1/v16i1 representing 4/2/1 bits. As far as I understand, when llvm says "store this v4i1", it really does need to store 4 bits (or 8, that being the size of a byte, with this bottom 4 as the interesting bits). For example a bitcast from a v8i1 to a i8 is defined as a store followed by a load, which is how the code is expanded. So this instead lowers the v4i1/v8i1 load/store through some shuffles to get the bits into the correct positions. This, as you might imagine, is not as efficient as a single instruction. But I believe it is needed for correctness. v16i1 equally should not load/store 32bits, only storing the 16bits of data. Stack loads/stores are still using the VSTR_P0 (as can be seen by the test not changing). This is fine as they are self-consistent, it is only "externally observable loads/stores" (from our point of view) that need to be corrected. Differential revision: https://reviews.llvm.org/D67085
  10. AMDGPU/GlobalISel: Select atomic loads A new check for an explicitly atomic MMO is needed to avoid incorrectly matching pattern for non-atomic loads
  11. AMDGPU/GlobalISel: Fix RegBankSelect for unaligned, uniform constant loads
  12. Fix typo in comment noticed in D60295. NFCI.
  13. AMDGPU/GlobalISel: Fix regbankselect for uniform extloads There are no scalar extloads.
  14. AMDGPU: Remove code address space predicates Fixes 8-byte, 8-byte aligned LDS loads. 16-byte case still broken due to not be reported as legal.
  15. AMDGPU/GlobalISel: Select G_PTR_MASK
  16. AMDGPU/GlobalISel: Fix reg bank for uniform LDS loads The pointer is always a VGPR. Also fix hardcoding the pointer size to 64.
  17. [NFC] Add aacps bitfields access test
  18. AMDGPU/GlobalISel: Use known bits for selection
  19. [clangd] Use pre-populated mappings for standard symbols Summary: This takes ~5% of time when running clangd unit tests. To achieve this, move mapping of system includes out of CanonicalIncludes and into a separate class Reviewers: sammccall, hokein Reviewed By: sammccall Subscribers: MaskRay, jkorous, arphaman, kadircet, jfb, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D67172
  20. AMDGPU/GlobalISel: Legalize wavefrontsize intrinsic
  21. AMDGPU/GlobalISel: Try generated matcher before add/sub code This will allow optimization patterns which fold adds away to work.
  22. [ARM] Remove some spurious MVE reduction instructions. The family of 'dual-accumulating' vector multiply-add instructions (VMLADAV, VMLALDAV and VRMLALDAVH) can all operate on both signed and unsigned integer types, and they all have an 'exchange' variant (with an X in the name) that modifies which pairs of vector lanes in the two inputs are multiplied together. But there's a clause in the spec that says that the X variants //don't// operate on unsigned integer types, only signed. You can have X, or unsigned, or neither, but not both. We didn't notice that clause when we implemented the MC support for these instructions, so LLVM believes that things like VMLADAVX.U8 do exist, contradicting the spec. Here I fix that by conditioning them out in Tablegen. In order to do that, I've reversed the nesting order of the Tablegen multiclasses for those instructions. Previously, the innermost multiclass generated the X and not-X variants, and the one outside that generated the A and not-A variants. Now X is done by the outer multiclass, which allows me to bypass that one when I only want the two not-X variants. Changing the multiclass nesting order also changes the names of the instruction ids unless I make a special effort not to. I decided that while I was changing them anyway I'd make them look nicer; so now the instructions have names like MVE_VMLADAVs32 or MVE_VMLADAVaxs32, instead of cumbersome _noacc_noexch suffixes. The corresponding multiply-subtract instructions are unaffected. Those don't accept unsigned types at all, either in the spec or in LLVM. Reviewers: ostannard, dmgreen Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67214
  23. AMDGPU/GlobalISel: Remove dead patterns
  24. Merge note_ovl_builtin_candidate diagnostics; NFC There is no difference between the unary and binary case, so merge them.
  25. [clangd] Add a new highlighting kind for typedefs Summary: We still attempt to highlight them as underlying types, but fallback to the generic 'typedef' highlighting kind if the underlying type is too complicated. Reviewers: hokein Reviewed By: hokein Subscribers: nridge, MaskRay, jkorous, arphaman, kadircet, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D67290
  26. [NFC][InstCombine] Fixup test i added in rL371352.
  27. compiler-rt: use fp_t instead of long double, for consistency Most builtins accepting or returning long double use the fp_t typedef. Change the remaining few cases to do so. Differential Revision: https://reviews.llvm.org/D35034
  28. [DFAPacketizer] Reapply: Track resources for packetized instructions Reapply with fix to reduce resources required by the compiler - use unsigned[2] instead of std::pair. This causes clang and gcc to compile the generated file multiple times faster, and hopefully will reduce the resource requirements on Visual Studio also. This fix is a little ugly but it's clearly the same issue the previous author of DFAPacketizer faced (the previous tables use unsigned[2] rather uglily too). This patch allows the DFAPacketizer to be queried after a packet is formed to work out which resources were allocated to the packetized instructions. This is particularly important for targets that do their own bundle packing - it's not sufficient to know simply that instructions can share a packet; which slots are used is also required for encoding. This extends the emitter to emit a side-table containing resource usage diffs for each state transition. The packetizer maintains a set of all possible resource states in its current state. After packetization is complete, all remaining resource states are possible packetization strategies. The sidetable is only ~500K for Hexagon, but the extra tracking is disabled by default (most uses of the packetizer like MachinePipeliner don't care and don't need the extra maintained state). Differential Revision: https://reviews.llvm.org/D66936
  29. [Inliner][NFC] Make test less brittle. Summary: This tests inlining size thresholds, but relies on the output of running the full O2 pipeline, making it brittle against changes in unrelated passes. Only run the inlining pass and set thresholds on the test RUN line instead. Found while investigating D60318. Reviewers: RKSimon, qcolombet Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67349
  30. [clang-tidy] Fix bug in bugprone-use-after-move check Summary: The bugprone-use-after-move check exhibits false positives for certain uses of the C++17 if/switch init statements. These false positives are caused by a bug in the ExprSequence calculations. This revision adds tests for the false positives and fixes the corresponding sequence calculation. Reviewers: gribozavr Subscribers: xazax.hun, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D67292
  31. [ARM][MVE] VCTP instruction selection Add codegen support for vctp{8,16,32}. Differential Revision: https://reviews.llvm.org/D67344
  32. [clang-doc] sys::fs::F_None -> OF_None. NFC F_None, F_Text and F_Append are kept for compatibility.
  33. Revert rL371198 from llvm/trunk: [DFAPacketizer] Track resources for packetized instructions This patch allows the DFAPacketizer to be queried after a packet is formed to work out which resources were allocated to the packetized instructions. This is particularly important for targets that do their own bundle packing - it's not sufficient to know simply that instructions can share a packet; which slots are used is also required for encoding. This extends the emitter to emit a side-table containing resource usage diffs for each state transition. The packetizer maintains a set of all possible resource states in its current state. After packetization is complete, all remaining resource states are possible packetization strategies. The sidetable is only ~500K for Hexagon, but the extra tracking is disabled by default (most uses of the packetizer like MachinePipeliner don't care and don't need the extra maintained state). Differential Revision: https://reviews.llvm.org/D66936 ........ Reverted as this is causing "compiler out of heap space" errors on MSVC 2017/19 NDEBUG builds
  34. [clangd] Support multifile edits as output of Tweaks Summary: First patch for propogating multifile changes from tweak outputs to LSP WorkspaceEdits. Uses SM to convert tooling::Replacements to TextEdits. Errors out if there are any inconsistencies between the draft version and the version generated the edits. Reviewers: sammccall Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D66637
Revision 371427 by arsenm:
AMDGPU: Move MnemonicAlias out of instruction def hierarchy

Unfortunately MnemonicAlias defines a "Predicates" field just like an
instruction or pattern, with a somewhat different interpretation.

This ends up overriding the intended Predicates set by
PredicateControl on the pseudoinstruction defintions with an empty
list. This allowed incorrectly selecting instructions that should have
been rejected due to the SubtargetPredicate from patterns on the
instruction definition.

This does remove the divergent predicate from the 64-bit shift
patterns, which were already not used for the 32-bit shift, so I'm not
sure what the point was. This also removes a second, redundant copy of
the 64-bit divergent patterns.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.tdllvm.src/lib/Target/AMDGPU/VOP1Instructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.tdllvm.src/lib/Target/AMDGPU/VOP2Instructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.tdllvm.src/lib/Target/AMDGPU/VOP3Instructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/VOPInstructions.tdllvm.src/lib/Target/AMDGPU/VOPInstructions.td
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir
Revision 371426 by spatel:
[SLP] add test for over-vectorization (PR33958); NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/SLPVectorizer/X86/consecutive-access.llllvm.src/test/Transforms/SLPVectorizer/X86/consecutive-access.ll
Revision 371425 by paquette:
[GlobalISel][AArch64] Handle tail calls with non-void return types

Just return once you emit the call, which is exactly what SelectionDAG does in
this situation.

Update call-translator-tail-call.ll.

Also update dllimport.ll to show that we tail call here in GISel again. Add
-verify-machineinstrs to the GISel line too, to defend against verifier
failures.

Differential revision: https://reviews.llvm.org/D67282
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cppllvm.src/lib/Target/AArch64/AArch64CallLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.llllvm.src/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
The file was modified/llvm/trunk/test/CodeGen/AArch64/dllimport.llllvm.src/test/CodeGen/AArch64/dllimport.ll
Revision 371424 by arsenm:
AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE

Handle the simple case that lowers to a constant.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cppllvm.src/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.hllvm.src/lib/Target/AMDGPU/AMDGPUISelLowering.h
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cppllvm.src/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.hllvm.src/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cppllvm.src/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/lds-global-non-entry-func.llllvm.src/test/CodeGen/AMDGPU/GlobalISel/lds-global-non-entry-func.ll
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.llllvm.src/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/lds-size.llllvm.src/test/CodeGen/AMDGPU/GlobalISel/lds-size.ll
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.llllvm.src/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
Revision 371423 by arsenm:
AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR_TRUNC

Treat this as legal on gfx9 since it can use S_PACK_* instructions for
this.

This isn't used by anything yet. The same will probably apply to
16-bit G_BUILD_VECTOR without the trunc.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cppllvm.src/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cppllvm.src/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.hllvm.src/lib/Target/AMDGPU/AMDGPUSubtarget.h
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-trunc.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-trunc.mir
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector-trunc.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector-trunc.mir
Revision 371422 by ibiryukov:
[clangd] Attempt to fix failing Windows buildbots.

The assertion is failing on Windows, probably because path separator is different.

For the failure see:
http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast/builds/28072/steps/test/logs/stdio
Change TypePath in RepositoryPath in Workspace
The file was modified/clang-tools-extra/trunk/clangd/index/CanonicalIncludes.cppclang-tools-extra.src/clangd/index/CanonicalIncludes.cpp
Revision 371421 by gribozavr:
Revert "[MachineCopyPropagation] Remove redundant copies after TailDup via machine-cp"

This reverts commit 371359. I'm suspecting a miscompile, I posted a
reproducer to https://reviews.llvm.org/D65267.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/MachineCopyPropagation.cppllvm.src/lib/CodeGen/MachineCopyPropagation.cpp
The file was modified/llvm/trunk/test/CodeGen/PowerPC/redundant-copy-after-tail-dup.llllvm.src/test/CodeGen/PowerPC/redundant-copy-after-tail-dup.ll
The file was modified/llvm/trunk/test/CodeGen/X86/mul-i512.llllvm.src/test/CodeGen/X86/mul-i512.ll
The file was modified/llvm/trunk/test/CodeGen/X86/umulo-128-legalisation-lowering.llllvm.src/test/CodeGen/X86/umulo-128-legalisation-lowering.ll
Revision 371420 by maskray:
[yaml2obj] Simplify p_filesz/p_memsz computing

This fixes a bug as well. When "FileSize:" (p_filesz) is specified and
different from the actual value, the following code probably should not
use PHeader.p_filesz:

  if (SHeader->sh_offset == PHeader.p_offset + PHeader.p_filesz)
    PHeader.p_memsz += SHeader->sh_size;

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D67256
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/ObjectYAML/ELFEmitter.cppllvm.src/lib/ObjectYAML/ELFEmitter.cpp
The file was modified/llvm/trunk/test/tools/yaml2obj/program-header-size-offset.yamlllvm.src/test/tools/yaml2obj/program-header-size-offset.yaml
Revision 371419 by dmgreen:
[ARM] Fix loads and stores for predicate vectors

These predicate vectors can usually be loaded and stored with a single
instruction, a VSTR_P0. However this instruction will store the entire P0
predicate, 16 bits, zeroextended to 32bits. Each lane of the the
v4i1/v8i1/v16i1 representing 4/2/1 bits.

As far as I understand, when llvm says "store this v4i1", it really does need
to store 4 bits (or 8, that being the size of a byte, with this bottom 4 as the
interesting bits). For example a bitcast from a v8i1 to a i8 is defined as a
store followed by a load, which is how the code is expanded.

So this instead lowers the v4i1/v8i1 load/store through some shuffles to get
the bits into the correct positions. This, as you might imagine, is not as
efficient as a single instruction. But I believe it is needed for correctness.
v16i1 equally should not load/store 32bits, only storing the 16bits of data.
Stack loads/stores are still using the VSTR_P0 (as can be seen by the test not
changing). This is fine as they are self-consistent, it is only "externally
observable loads/stores" (from our point of view) that need to be corrected.

Differential revision: https://reviews.llvm.org/D67085
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/ARM/ARMISelLowering.cppllvm.src/lib/Target/ARM/ARMISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/ARM/ARMInstrMVE.tdllvm.src/lib/Target/ARM/ARMInstrMVE.td
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-masked-ldst.llllvm.src/test/CodeGen/Thumb2/mve-masked-ldst.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-masked-load.llllvm.src/test/CodeGen/Thumb2/mve-masked-load.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-masked-store.llllvm.src/test/CodeGen/Thumb2/mve-masked-store.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-pred-bitcast.llllvm.src/test/CodeGen/Thumb2/mve-pred-bitcast.ll
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-pred-loadstore.llllvm.src/test/CodeGen/Thumb2/mve-pred-loadstore.ll
Revision 371418 by arsenm:
AMDGPU/GlobalISel: Select atomic loads

A new check for an explicitly atomic MMO is needed to avoid
incorrectly matching pattern for non-atomic loads
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.tdllvm.src/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUGISel.tdllvm.src/lib/Target/AMDGPU/AMDGPUGISel.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.tdllvm.src/lib/Target/AMDGPU/SIInstrInfo.td
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.llllvm.src/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
The file was modified/llvm/trunk/utils/TableGen/GlobalISelEmitter.cppllvm.src/utils/TableGen/GlobalISelEmitter.cpp
Revision 371416 by arsenm:
AMDGPU/GlobalISel: Fix RegBankSelect for unaligned, uniform constant loads
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cppllvm.src/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
Revision 371415 by rksimon:
Fix typo in comment noticed in D60295. NFCI.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/SwitchLoweringUtils.hllvm.src/include/llvm/CodeGen/SwitchLoweringUtils.h
Revision 371414 by arsenm:
AMDGPU/GlobalISel: Fix regbankselect for uniform extloads

There are no scalar extloads.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cppllvm.src/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
Revision 371413 by arsenm:
AMDGPU: Remove code address space predicates

Fixes 8-byte, 8-byte aligned LDS loads. 16-byte case still broken due
to not be reported as legal.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUGISel.tdllvm.src/lib/Target/AMDGPU/AMDGPUGISel.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/DSInstructions.tdllvm.src/lib/Target/AMDGPU/DSInstructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.tdllvm.src/lib/Target/AMDGPU/SIInstrInfo.td
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
The file was modified/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cppllvm.src/utils/TableGen/CodeGenDAGPatterns.cpp
Revision 371412 by arsenm:
AMDGPU/GlobalISel: Select G_PTR_MASK
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cppllvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.hllvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cppllvm.src/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-mask.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-mask.mir
Revision 371411 by arsenm:
AMDGPU/GlobalISel: Fix reg bank for uniform LDS loads

The pointer is always a VGPR. Also fix hardcoding the pointer size to
64.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cppllvm.src/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
Revision 371410 by dnsampaio:
[NFC] Add aacps bitfields access test
Change TypePath in RepositoryPath in Workspace
The file was added/cfe/trunk/test/CodeGen/aapcs-bitfield.cclang.src/test/CodeGen/aapcs-bitfield.c
Revision 371409 by arsenm:
AMDGPU/GlobalISel: Use known bits for selection
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cppllvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
Revision 371408 by ibiryukov:
[clangd] Use pre-populated mappings for standard symbols

Summary:
This takes ~5% of time when running clangd unit tests.

To achieve this, move mapping of system includes out of CanonicalIncludes
and into a separate class

Reviewers: sammccall, hokein

Reviewed By: sammccall

Subscribers: MaskRay, jkorous, arphaman, kadircet, jfb, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D67172
Change TypePath in RepositoryPath in Workspace
The file was modified/clang-tools-extra/trunk/clangd/ParsedAST.cppclang-tools-extra.src/clangd/ParsedAST.cpp
The file was modified/clang-tools-extra/trunk/clangd/Preamble.cppclang-tools-extra.src/clangd/Preamble.cpp
The file was modified/clang-tools-extra/trunk/clangd/index/CanonicalIncludes.cppclang-tools-extra.src/clangd/index/CanonicalIncludes.cpp
The file was modified/clang-tools-extra/trunk/clangd/index/CanonicalIncludes.hclang-tools-extra.src/clangd/index/CanonicalIncludes.h
The file was modified/clang-tools-extra/trunk/clangd/index/IndexAction.cppclang-tools-extra.src/clangd/index/IndexAction.cpp
The file was modified/clang-tools-extra/trunk/clangd/unittests/CanonicalIncludesTests.cppclang-tools-extra.src/clangd/unittests/CanonicalIncludesTests.cpp
The file was modified/clang-tools-extra/trunk/clangd/unittests/SymbolCollectorTests.cppclang-tools-extra.src/clangd/unittests/SymbolCollectorTests.cpp
Revision 371407 by arsenm:
AMDGPU/GlobalISel: Legalize wavefrontsize intrinsic
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cppllvm.src/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.wavefrontsize.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.wavefrontsize.mir
Revision 371406 by arsenm:
AMDGPU/GlobalISel: Try generated matcher before add/sub code

This will allow optimization patterns which fold adds away to work.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cppllvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Revision 371405 by statham:
[ARM] Remove some spurious MVE reduction instructions.

The family of 'dual-accumulating' vector multiply-add instructions
(VMLADAV, VMLALDAV and VRMLALDAVH) can all operate on both signed and
unsigned integer types, and they all have an 'exchange' variant (with
an X in the name) that modifies which pairs of vector lanes in the two
inputs are multiplied together. But there's a clause in the spec that
says that the X variants //don't// operate on unsigned integer types,
only signed. You can have X, or unsigned, or neither, but not both.

We didn't notice that clause when we implemented the MC support for
these instructions, so LLVM believes that things like VMLADAVX.U8 do
exist, contradicting the spec. Here I fix that by conditioning them
out in Tablegen.

In order to do that, I've reversed the nesting order of the Tablegen
multiclasses for those instructions. Previously, the innermost
multiclass generated the X and not-X variants, and the one outside
that generated the A and not-A variants. Now X is done by the outer
multiclass, which allows me to bypass that one when I only want the
two not-X variants.

Changing the multiclass nesting order also changes the names of the
instruction ids unless I make a special effort not to. I decided that
while I was changing them anyway I'd make them look nicer; so now the
instructions have names like MVE_VMLADAVs32 or MVE_VMLADAVaxs32,
instead of cumbersome _noacc_noexch suffixes.

The corresponding multiply-subtract instructions are unaffected. Those
don't accept unsigned types at all, either in the spec or in LLVM.

Reviewers: ostannard, dmgreen

Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67214
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/ARM/ARMInstrMVE.tdllvm.src/lib/Target/ARM/ARMInstrMVE.td
The file was modified/llvm/trunk/test/MC/ARM/mve-reductions.sllvm.src/test/MC/ARM/mve-reductions.s
The file was modified/llvm/trunk/test/MC/Disassembler/ARM/mve-reductions.txtllvm.src/test/MC/Disassembler/ARM/mve-reductions.txt
Revision 371404 by arsenm:
AMDGPU/GlobalISel: Remove dead patterns
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUGISel.tdllvm.src/lib/Target/AMDGPU/AMDGPUGISel.td
Revision 371403 by svenvh:
Merge note_ovl_builtin_candidate diagnostics; NFC

There is no difference between the unary and binary case, so
merge them.
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.tdclang.src/include/clang/Basic/DiagnosticSemaKinds.td
The file was modified/cfe/trunk/lib/Sema/SemaOverload.cppclang.src/lib/Sema/SemaOverload.cpp
Revision 371402 by ibiryukov:
[clangd] Add a new highlighting kind for typedefs

Summary:
We still attempt to highlight them as underlying types, but fallback to
the generic 'typedef' highlighting kind if the underlying type is too
complicated.

Reviewers: hokein

Reviewed By: hokein

Subscribers: nridge, MaskRay, jkorous, arphaman, kadircet, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D67290
Change TypePath in RepositoryPath in Workspace
The file was modified/clang-tools-extra/trunk/clangd/SemanticHighlighting.cppclang-tools-extra.src/clangd/SemanticHighlighting.cpp
The file was modified/clang-tools-extra/trunk/clangd/SemanticHighlighting.hclang-tools-extra.src/clangd/SemanticHighlighting.h
The file was modified/clang-tools-extra/trunk/clangd/test/semantic-highlighting.testclang-tools-extra.src/clangd/test/semantic-highlighting.test
The file was modified/clang-tools-extra/trunk/clangd/unittests/SemanticHighlightingTests.cppclang-tools-extra.src/clangd/unittests/SemanticHighlightingTests.cpp
Revision 371401 by lebedevri:
[NFC][InstCombine] Fixup test i added in rL371352.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/InstCombine/result-of-usub-is-non-zero-and-no-overflow.llllvm.src/test/Transforms/InstCombine/result-of-usub-is-non-zero-and-no-overflow.ll
Revision 371400 by emaste:
compiler-rt: use fp_t instead of long double, for consistency

Most builtins accepting or returning long double use the fp_t typedef.
Change the remaining few cases to do so.

Differential Revision: https://reviews.llvm.org/D35034
Change TypePath in RepositoryPath in Workspace
The file was modified/compiler-rt/trunk/lib/builtins/addtf3.ccompiler-rt.src/lib/builtins/addtf3.c
The file was modified/compiler-rt/trunk/lib/builtins/divtf3.ccompiler-rt.src/lib/builtins/divtf3.c
The file was modified/compiler-rt/trunk/lib/builtins/extenddftf2.ccompiler-rt.src/lib/builtins/extenddftf2.c
The file was modified/compiler-rt/trunk/lib/builtins/extendsftf2.ccompiler-rt.src/lib/builtins/extendsftf2.c
Revision 371399 by jamesm:
[DFAPacketizer] Reapply: Track resources for packetized instructions

Reapply with fix to reduce resources required by the compiler - use
unsigned[2] instead of std::pair. This causes clang and gcc to compile
the generated file multiple times faster, and hopefully will reduce
the resource requirements on Visual Studio also. This fix is a little
ugly but it's clearly the same issue the previous author of
DFAPacketizer faced (the previous tables use unsigned[2] rather uglily
too).

This patch allows the DFAPacketizer to be queried after a packet is formed to work out which
resources were allocated to the packetized instructions.

This is particularly important for targets that do their own bundle packing - it's not
sufficient to know simply that instructions can share a packet; which slots are used is
also required for encoding.

This extends the emitter to emit a side-table containing resource usage diffs for each
state transition. The packetizer maintains a set of all possible resource states in its
current state. After packetization is complete, all remaining resource states are
possible packetization strategies.

The sidetable is only ~500K for Hexagon, but the extra tracking is disabled by default
(most uses of the packetizer like MachinePipeliner don't care and don't need the extra
maintained state).

Differential Revision: https://reviews.llvm.org/D66936
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/DFAPacketizer.hllvm.src/include/llvm/CodeGen/DFAPacketizer.h
The file was modified/llvm/trunk/lib/CodeGen/DFAPacketizer.cppllvm.src/lib/CodeGen/DFAPacketizer.cpp
The file was modified/llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cppllvm.src/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
The file was added/llvm/trunk/test/CodeGen/Hexagon/packetizer-resources.llllvm.src/test/CodeGen/Hexagon/packetizer-resources.ll
The file was modified/llvm/trunk/utils/TableGen/DFAPacketizerEmitter.cppllvm.src/utils/TableGen/DFAPacketizerEmitter.cpp
Revision 371397 by courbet:
[Inliner][NFC] Make test less brittle.

Summary:
This tests inlining size thresholds, but relies on the output of running
the full O2 pipeline, making it brittle against changes in unrelated
passes.

Only run the inlining pass and set thresholds on the test RUN line
instead.

Found while investigating D60318.

Reviewers: RKSimon, qcolombet

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67349
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/Inline/inline_minisize.llllvm.src/test/Transforms/Inline/inline_minisize.ll
Revision 371396 by ymandel:
[clang-tidy] Fix bug in bugprone-use-after-move check

Summary:
The bugprone-use-after-move check exhibits false positives for certain uses of
the C++17 if/switch init statements. These false positives are caused by a bug
in the ExprSequence calculations.

This revision adds tests for the false positives and fixes the corresponding
sequence calculation.

Reviewers: gribozavr

Subscribers: xazax.hun, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D67292
Change TypePath in RepositoryPath in Workspace
The file was modified/clang-tools-extra/trunk/clang-tidy/utils/ExprSequence.cppclang-tools-extra.src/clang-tidy/utils/ExprSequence.cpp
The file was modified/clang-tools-extra/trunk/test/clang-tidy/bugprone-use-after-move.cppclang-tools-extra.src/test/clang-tidy/bugprone-use-after-move.cpp
Revision 371395 by sam_parker:
[ARM][MVE] VCTP instruction selection
   
Add codegen support for vctp{8,16,32}.

Differential Revision: https://reviews.llvm.org/D67344
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/ARM/ARMInstrMVE.tdllvm.src/lib/Target/ARM/ARMInstrMVE.td
The file was added/llvm/trunk/test/CodeGen/Thumb2/mve-vctp.llllvm.src/test/CodeGen/Thumb2/mve-vctp.ll
Revision 371394 by maskray:
[clang-doc] sys::fs::F_None -> OF_None. NFC

F_None, F_Text and F_Append are kept for compatibility.
Change TypePath in RepositoryPath in Workspace
The file was modified/clang-tools-extra/trunk/clang-doc/HTMLGenerator.cppclang-tools-extra.src/clang-doc/HTMLGenerator.cpp
The file was modified/clang-tools-extra/trunk/clang-doc/tool/ClangDocMain.cppclang-tools-extra.src/clang-doc/tool/ClangDocMain.cpp
Revision 371393 by rksimon:
Revert rL371198 from llvm/trunk: [DFAPacketizer] Track resources for packetized instructions

This patch allows the DFAPacketizer to be queried after a packet is formed to work out which
resources were allocated to the packetized instructions.

This is particularly important for targets that do their own bundle packing - it's not
sufficient to know simply that instructions can share a packet; which slots are used is
also required for encoding.

This extends the emitter to emit a side-table containing resource usage diffs for each
state transition. The packetizer maintains a set of all possible resource states in its
current state. After packetization is complete, all remaining resource states are
possible packetization strategies.

The sidetable is only ~500K for Hexagon, but the extra tracking is disabled by default
(most uses of the packetizer like MachinePipeliner don't care and don't need the extra
maintained state).

Differential Revision: https://reviews.llvm.org/D66936
........
Reverted as this is causing "compiler out of heap space" errors on MSVC 2017/19 NDEBUG builds
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/DFAPacketizer.hllvm.src/include/llvm/CodeGen/DFAPacketizer.h
The file was modified/llvm/trunk/lib/CodeGen/DFAPacketizer.cppllvm.src/lib/CodeGen/DFAPacketizer.cpp
The file was modified/llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cppllvm.src/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
The file was removed/llvm/trunk/test/CodeGen/Hexagon/packetizer-resources.llllvm.src/test/CodeGen/Hexagon/packetizer-resources.ll
The file was modified/llvm/trunk/utils/TableGen/DFAPacketizerEmitter.cppllvm.src/utils/TableGen/DFAPacketizerEmitter.cpp
Revision 371392 by kadircet:
[clangd] Support multifile edits as output of Tweaks

Summary:
First patch for propogating multifile changes from tweak outputs to LSP
WorkspaceEdits.

Uses SM to convert tooling::Replacements to TextEdits.
Errors out if there are any inconsistencies between the draft version and the
version generated the edits.

Reviewers: sammccall

Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D66637
Change TypePath in RepositoryPath in Workspace
The file was modified/clang-tools-extra/trunk/clangd/ClangdLSPServer.cppclang-tools-extra.src/clangd/ClangdLSPServer.cpp
The file was modified/clang-tools-extra/trunk/clangd/ClangdServer.cppclang-tools-extra.src/clangd/ClangdServer.cpp
The file was modified/clang-tools-extra/trunk/clangd/SourceCode.cppclang-tools-extra.src/clangd/SourceCode.cpp
The file was modified/clang-tools-extra/trunk/clangd/SourceCode.hclang-tools-extra.src/clangd/SourceCode.h
The file was modified/clang-tools-extra/trunk/clangd/refactor/Tweak.cppclang-tools-extra.src/clangd/refactor/Tweak.cpp
The file was modified/clang-tools-extra/trunk/clangd/refactor/Tweak.hclang-tools-extra.src/clangd/refactor/Tweak.h
The file was modified/clang-tools-extra/trunk/clangd/refactor/tweaks/AnnotateHighlightings.cppclang-tools-extra.src/clangd/refactor/tweaks/AnnotateHighlightings.cpp
The file was modified/clang-tools-extra/trunk/clangd/refactor/tweaks/ExpandAutoType.cppclang-tools-extra.src/clangd/refactor/tweaks/ExpandAutoType.cpp
The file was modified/clang-tools-extra/trunk/clangd/refactor/tweaks/ExpandMacro.cppclang-tools-extra.src/clangd/refactor/tweaks/ExpandMacro.cpp
The file was modified/clang-tools-extra/trunk/clangd/refactor/tweaks/ExtractFunction.cppclang-tools-extra.src/clangd/refactor/tweaks/ExtractFunction.cpp
The file was modified/clang-tools-extra/trunk/clangd/refactor/tweaks/ExtractVariable.cppclang-tools-extra.src/clangd/refactor/tweaks/ExtractVariable.cpp
The file was modified/clang-tools-extra/trunk/clangd/refactor/tweaks/RawStringLiteral.cppclang-tools-extra.src/clangd/refactor/tweaks/RawStringLiteral.cpp
The file was modified/clang-tools-extra/trunk/clangd/refactor/tweaks/SwapIfBranches.cppclang-tools-extra.src/clangd/refactor/tweaks/SwapIfBranches.cpp
The file was modified/clang-tools-extra/trunk/clangd/unittests/TweakTesting.cppclang-tools-extra.src/clangd/unittests/TweakTesting.cpp
The file was modified/clang-tools-extra/trunk/clangd/unittests/TweakTests.cppclang-tools-extra.src/clangd/unittests/TweakTests.cpp