FailedChanges

Summary

  1. [ARM] ACLE Chapter 9 intrinsics Implemented the remaining integer data processing intrinsics from the ARM ACLE v2.1 spec, such as parallel arithemtic and DSP style multiplications. Differential Revision: https://reviews.llvm.org/D32282
  2. Dummy commit to trigger CMake reconfiguration and unbreak Sphinx build
  3. Fix incorrect usage of __libcpp_mutex_trylock. Patch from Andrey Khalyavin
  4. Update Appveyor bot link to point to new llvm-mirror Appveyor account
  5. [X86][AVX-512] Allow EVEX encoded instruction selection when available for mul v8i32. Differential Revision: https://reviews.llvm.org/D32679
  6. [ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281
  7. [OpenCL] Add intel_reqd_sub_group_size attribute support Summary: Add intel_reqd_sub_group_size attribute support as intel extension cl_intel_required_subgroup_size from https://www.khronos.org/registry/OpenCL/extensions/intel/cl_intel_required_subgroup_size.txt Reviewers: Anastasia, bader, hfinkel, pxli168 Reviewed By: Anastasia, bader, pxli168 Subscribers: cfe-commits, yaxunl Differential Revision: https://reviews.llvm.org/D30805
  8. [X86] Disabling PLT in Regcall CC Functions According to psABI, PLT stub clobbers XMM8-XMM15. In Regcall calling convention those registers are used for passing parameters. Thus we need to prevent lazy binding in Regcall. Differential Revision: https://reviews.llvm.org/D32430
Revision 302131 by sam_parker:
[ARM] ACLE Chapter 9 intrinsics

Implemented the remaining integer data processing intrinsics from
the ARM ACLE v2.1 spec, such as parallel arithemtic and DSP style
multiplications.

Differential Revision: https://reviews.llvm.org/D32282
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/include/clang/Basic/BuiltinsARM.def (diff)llvm-revision.src/cfe/trunk/include/clang/Basic/BuiltinsARM.def
The file was modified/cfe/trunk/lib/Headers/arm_acle.h (diff)llvm-revision.src/cfe/trunk/lib/Headers/arm_acle.h
The file was modified/cfe/trunk/test/CodeGen/arm_acle.c (diff)llvm-revision.src/cfe/trunk/test/CodeGen/arm_acle.c
Revision 302130 by ericwf:
Dummy commit to trigger CMake reconfiguration and unbreak Sphinx build
Change TypePath in RepositoryPath in Workspace
The file was modified/lld/trunk/CMakeLists.txt (diff)llvm-revision.src/lld/trunk/CMakeLists.txt
Revision 302129 by ericwf:
Fix incorrect usage of __libcpp_mutex_trylock. Patch from Andrey Khalyavin
Change TypePath in RepositoryPath in Workspace
The file was modified/libcxx/trunk/src/memory.cpp (diff)llvm-revision.src/libcxx/trunk/src/memory.cpp
Revision 302128 by ericwf:
Update Appveyor bot link to point to new llvm-mirror Appveyor account
Change TypePath in RepositoryPath in Workspace
The file was modified/libcxx/trunk/docs/index.rst (diff)llvm-revision.src/libcxx/trunk/docs/index.rst
Revision 302127 by ibreger:
[X86][AVX-512] Allow EVEX encoded instruction selection when available for mul v8i32.

Differential Revision: https://reviews.llvm.org/D32679
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86InstrSSE.td (diff)llvm-revision.src/llvm/trunk/lib/Target/X86/X86InstrSSE.td
The file was modified/llvm/trunk/test/CodeGen/X86/avx-isa-check.ll (diff)llvm-revision.src/llvm/trunk/test/CodeGen/X86/avx-isa-check.ll
The file was modified/llvm/trunk/test/CodeGen/X86/avx512vl-arith.ll (diff)llvm-revision.src/llvm/trunk/test/CodeGen/X86/avx512vl-arith.ll
Revision 302126 by sam_parker:
[ARM] ACLE Chapter 9 intrinsics

Added the integer data processing intrinsics from ACLE v2.1 Chapter 9
but I have missed out the saturation_occurred intrinsics for now. For
the instructions that read and write the GE bits, a chain is included
and the only instruction that reads these flags (sel) is only
selectable via the implemented intrinsic.

Differential Revision: https://reviews.llvm.org/D32281
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/IR/IntrinsicsARM.td (diff)llvm-revision.src/llvm/trunk/include/llvm/IR/IntrinsicsARM.td
The file was modified/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (diff)llvm-revision.src/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/ARM/ARMISelLowering.h (diff)llvm-revision.src/llvm/trunk/lib/Target/ARM/ARMISelLowering.h
The file was modified/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (diff)llvm-revision.src/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
The file was modified/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (diff)llvm-revision.src/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
The file was added/llvm/trunk/test/CodeGen/ARM/acle-intrinsics-v5.llllvm-revision.src/llvm/trunk/test/CodeGen/ARM/acle-intrinsics-v5.ll
The file was added/llvm/trunk/test/CodeGen/ARM/acle-intrinsics.llllvm-revision.src/llvm/trunk/test/CodeGen/ARM/acle-intrinsics.ll
The file was removed/llvm/trunk/test/CodeGen/ARM/sat-arith.llllvm-revision.src/llvm/trunk/test/CodeGen/ARM/sat-arith.ll
Revision 302125 by pxl:
[OpenCL] Add intel_reqd_sub_group_size attribute support

Summary:
Add intel_reqd_sub_group_size attribute support as intel extension  cl_intel_required_subgroup_size from
https://www.khronos.org/registry/OpenCL/extensions/intel/cl_intel_required_subgroup_size.txt

Reviewers: Anastasia, bader, hfinkel, pxli168

Reviewed By: Anastasia, bader, pxli168

Subscribers: cfe-commits, yaxunl

Differential Revision: https://reviews.llvm.org/D30805
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/include/clang/Basic/Attr.td (diff)llvm-revision.src/cfe/trunk/include/clang/Basic/Attr.td
The file was modified/cfe/trunk/include/clang/Basic/AttrDocs.td (diff)llvm-revision.src/cfe/trunk/include/clang/Basic/AttrDocs.td
The file was modified/cfe/trunk/lib/CodeGen/CodeGenFunction.cpp (diff)llvm-revision.src/cfe/trunk/lib/CodeGen/CodeGenFunction.cpp
The file was modified/cfe/trunk/lib/CodeGen/CodeGenFunction.h (diff)llvm-revision.src/cfe/trunk/lib/CodeGen/CodeGenFunction.h
The file was modified/cfe/trunk/lib/Sema/SemaDeclAttr.cpp (diff)llvm-revision.src/cfe/trunk/lib/Sema/SemaDeclAttr.cpp
The file was modified/cfe/trunk/test/CodeGenOpenCL/kernel-attributes.cl (diff)llvm-revision.src/cfe/trunk/test/CodeGenOpenCL/kernel-attributes.cl
The file was modified/cfe/trunk/test/Misc/pragma-attribute-supported-attributes-list.test (diff)llvm-revision.src/cfe/trunk/test/Misc/pragma-attribute-supported-attributes-list.test
The file was modified/cfe/trunk/test/SemaOpenCL/invalid-kernel-attrs.cl (diff)llvm-revision.src/cfe/trunk/test/SemaOpenCL/invalid-kernel-attrs.cl
Revision 302124 by orenb:
[X86] Disabling PLT in Regcall CC Functions

According to psABI, PLT stub clobbers XMM8-XMM15.
In Regcall calling convention those registers are used for passing parameters.
Thus we need to prevent lazy binding in Regcall.

Differential Revision: https://reviews.llvm.org/D32430
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86Subtarget.cpp (diff)llvm-revision.src/llvm/trunk/lib/Target/X86/X86Subtarget.cpp
The file was added/llvm/trunk/test/CodeGen/X86/regcall-no-plt.llllvm-revision.src/llvm/trunk/test/CodeGen/X86/regcall-no-plt.ll