Started 1 mo 11 days ago
Took 17 hr on green-dragon-08

Failed Build #5466 (Sep 6, 2019 12:24:58 PM)

Revisions
  • http://llvm.org/svn/llvm-project/llvm/trunk : 371245
  • http://llvm.org/svn/llvm-project/cfe/trunk : 371241
  • http://llvm.org/svn/llvm-project/compiler-rt/trunk : 371003
  • http://llvm.org/svn/llvm-project/debuginfo-tests/trunk : 364589
  • http://llvm.org/svn/llvm-project/libcxx/trunk : 371131
  • http://llvm.org/svn/llvm-project/clang-tools-extra/trunk : 371194
Changes
  1. [ORC] Make sure RPC channel-send is called in blocking calls and responses.

    ORC-RPC batches calls by default, and the channel's send method must be called
    to transfer any buffered calls to the remote. The call to send was missing on
    responses and blocking calls in the SingleThreadedRPCEndpoint. This patch adds
    the necessary calls and modifies the RPC unit test to check for them. (detail/ViewSVN)
    by Lang Hames
  2. [llvm-jitlink] Add optional slab allocator for testing locality optimizations.

    The llvm-jitlink utility now accepts a '-slab-allocate <size>' option. If given,
    llvm-jitlink will use a slab-based memory manager rather than the default
    InProcessMemoryManager. Using a slab allocator will allow reliable testing of
    future locality based optimizations (e.g. PLT and GOT elimination) in JITLink.

    The <size> argument is a number, optionally followed by a units specifier (Kb,
    Mb, or Gb). If the units are not given then the number is assumed to be in Kb. (detail/ViewSVN)
    by Lang Hames
  3. [X86] Use MOVSX by default instead of CBW to extend i8 to AX for i8 sdivrem.

    We can use a MOVSX16 here then rely on FixupBWInst to change to
    MOVSX32 if the upper bits are dead. With a special case to
    not promote if it could be turned into CBW.

    Then we can rely on X86MCInstLower to turn the MOVSX into CBW
    very late if register allocation worked out.

    Using MOVSX gives an opportunity to use the MOVSX as a both a
    copy and a sign extend since the input and output register aren't
    tied together.

    Differential Revision: https://reviews.llvm.org/D67192 (detail/ViewSVN)
    by ctopper
  4. [X86] Use MOVZX16rr8/MOVZXrm8 when extending input for i8 udivrem.

    We can rely on X86FixupBWInsts to turn these into MOVZX32. This
    simplifies a follow up commit to use MOVSX for i8 sdivrem with
    a late optimization to use CBW when register allocation works out. (detail/ViewSVN)
    by ctopper
  5. [LifetimeAnalysis] don't use raw string literals in macros

    They broke the AArch64 bots (gcc does not support it) (detail/ViewSVN)
    by mgehre
  6. [X86] Teach FixupBWInsts to turn MOVSX16rr8/MOVZX16rr8/MOVSX16rm8/MOVZX16rm8 into their 32-bit dest equivalents when the upper part of the register is dead. (detail/ViewSVN)
    by ctopper
  7. [PowerPC][XCOFF] Verify symbol table in xcoff object files. [NFC]

    Extend the common/local-common testing for object files to also verify the
    symbol table now that the needed functionality has landed in llvm-readobj.

    Differential Revision: https://reviews.llvm.org/D66944 (detail/ViewSVN)
    by sfertile
  8. [ConstantFolding] Refactor functions not available before C99 (NFC)

    Note the cases when calling a function at compile time may fail if the host
    does not support the C99 run time library. (detail/ViewSVN)
    by evandro
  9. [FPEnv] Teach the IRBuilder about constrained FPToSI and FPToUI.

    The IRBuilder doesn't know that the two floating point to integer instructions
    have constrained equivalents. This patch adds the support by building on
    the strict FP mode now present in the IRBuilder.

    Reviewed by: John McCall
    Approved by: John McCall
    Differential Revision: https://reviews.llvm.org/D67291 (detail/ViewSVN)
    by kpn
  10. [Remarks] Add support for internalizing a remark in a string table

    In order to keep remarks around, we need to make them tied to a string
    table.

    Users then can delete the parser and rely on the string table to keep
    the memory of the strings alive and deduplicated. (detail/ViewSVN)
    by thegameg
  11. [ARM] Add patterns for VSUB with q and r registers

    Added patterns for VSUB to support q and r registers, which reduces
    pressure on q registers. (detail/ViewSVN)
    by oliverlars
  12. [ARM] Add patterns for VADD with q and r registers

    Added support for VADD to use q and r registers, which reduces pressure
    on q registers. (detail/ViewSVN)
    by oliverlars
  13. [ARM] Add patterns for VMUL with q and r registers

    Added support for VMUL to use an r register, this reduces pressure on
    the q registers. (detail/ViewSVN)
    by oliverlars
  14. [ConstantFolding] Refactor function match for better speed (NFC)

    Use an `enum` instead of string comparison to match the candidate function. (detail/ViewSVN)
    by evandro
  15. [AArch64][GlobalISel] Always fall back on tail calls with -tailcallopt

    -tailcallopt requires that we perform different stack adjustments than with
    sibling calls. For example, the `@caller_to0_from8` function in
    test/CodeGen/AArch64/tail-call.ll requires that we adjust SP. Without
    -tailcallopt, this adjustment does not happen. With it, however, it is expected.

    So, to ensure that adding sibling call support doesn't break -tailcallopt,
    make CallLowering always fall back on possible tail calls when -tailcallopt
    is passed in.

    Update test/CodeGen/AArch64/tail-call.ll with a GlobalISel line to make sure
    that we don't differ from the SDAG implementation at any point.

    Differential Revision: https://reviews.llvm.org/D67245 (detail/ViewSVN)
    by paquette
  16. [NFCI] Unbreak buildbots (detail/ViewSVN)
    by xbolva00
  17. [InstCombine] pow(x, +/- 0.0) -> 1.0

    Summary:
    This isn't an important optimization at all... We're already doing:
      pow(x, 0.0) -> 1.0
    My patch merely teaches instcombine that -0.0 does the same.

    However, doing this fixes an AMAZING bug! Compile this program:

      extern "C" double pow(double, double);
      double boom(double base) {
        return pow(base, -0.0);
      }

    With:
      clang++ ~/Desktop/fast-math.cpp -ffast-math -O2 -S

    And clang will crash with a signal. Wow, fast math is so fast it ICEs the
    compiler! Arguably, the generated math is infinitely fast.

    What's actually happening is that we recurse infinitely in getPow. In debug we
    hit its assertion:
      assert(Exp != 0 && "Incorrect exponent 0 not handled");

    We avoid this entire mess if we instead recognize that an exponent of positive
    and negative zero yield 1.0.

    A separate commit, r371221, fixed the same problem. This only contains the added
    tests.

    <rdar://problem/54598300>

    Reviewers: scanon

    Subscribers: hiraditya, jkorous, dexonsmith, ributzka, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D67248 (detail/ViewSVN)
    by jfb
  18. [NFC] Added new tests for r371222 (detail/ViewSVN)
    by xbolva00
  19. [Diagnostics] Refactor code for -Wsizeof-pointer-div, catch more cases; also add -Wsizeof-array-div

    Previously, -Wsizeof-pointer-div failed to catch:
    const int *r;
    sizeof(r) / sizeof(int);

    Now fixed.
    Also introduced -Wsizeof-array-div which catches bugs like:
    sizeof(r) / sizeof(short);

    (Array element type does not match type of sizeof operand). (detail/ViewSVN)
    by xbolva00
  20. [SimplifyLibCalls] handle pow(x,-0.0) before it can assert (PR43233)

    https://bugs.llvm.org/show_bug.cgi?id=43233 (detail/ViewSVN)
    by spatel
  21. [ARM] Sink add/mul(shufflevector(insertelement())) for MVE instruction selection

    This patch sinks add/mul(shufflevector(insertelement())) into the basic block in which they are used so that they can then be selected together.

    This is useful for various MVE instructions, such as vmla and others that take R registers.

    Loop tests have been added to the vmla test file to make sure vmlas are generated in loops.

    Differential revision: https://reviews.llvm.org/D66295 (detail/ViewSVN)
    by samtebbs
  22. [AMDGPU] Enable constant offset promotion to immediate operand for VMEM stores

    Differential revision: https://reviews.llvm.org/D66958 (detail/ViewSVN)
    by vpykhtin
  23. [Alignment][NFC] Use Align with TargetLowering::setPrefFunctionAlignment

    Summary:
    This is patch is part of a series to introduce an Alignment type.
    See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
    See this patch for the introduction of the type: https://reviews.llvm.org/D64790

    Reviewers: courbet

    Subscribers: nemanjai, javed.absar, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, s.egerton, pzheng, ychen, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D67267 (detail/ViewSVN)
    by gchatelet
  24. [Object] remove struct constructor, NFC

    Summary: make POD struct by removing ctors

    Reviewers: avl, dblaikie

    Reviewed By: dblaikie

    Subscribers: ributzka, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D67251 (detail/ViewSVN)
    by cishida
  25. [Alignment][NFC] Use Align with TargetLowering::setPrefLoopAlignment

    Summary:
    This is patch is part of a series to introduce an Alignment type.
    See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
    See this patch for the introduction of the type: https://reviews.llvm.org/D64790

    Reviewers: courbet

    Subscribers: nemanjai, hiraditya, kbarton, MaskRay, jsji, ychen, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D67278 (detail/ViewSVN)
    by gchatelet
  26. [NFC][CodeGen][UBSan] EmitCheckedInBoundsGEP(): pass a vector to EmitCheck()

    Will be easier to add a new 'check' in a follow-up.

    This was originally part of https://reviews.llvm.org/D67122 (detail/ViewSVN)
    by lebedevri
  27. [NFC][CodeGen][UBSan] EmitCheckedInBoundsGEP(): refactor EmitGEPOffsetInBytes() helper

    It shouldn't really be inlined into the EmitCheckedInBoundsGEP().
    Refactoring it beforehand will make follow-up changes more obvious.

    This was originally part of https://reviews.llvm.org/D67122 (detail/ViewSVN)
    by lebedevri
  28. [NFC][CodeGen][UBSan] EmitCheckedInBoundsGEP(): add some comments to pointer-overflow check

    It's rather eye-twiching, some comments may help here..

    This was originally part of https://reviews.llvm.org/D67122 (detail/ViewSVN)
    by lebedevri
  29. libclang depends on ClangDriverOptions since r352803

    Without this, the build would sometimes fail with

        In file included from clang/tools/libclang/CIndexer.cpp:17:
        In file included from clang/include/clang/Driver/Driver.h:15:
        clang/include/clang/Driver/Options.h:44:10: fatal error:
            'clang/Driver/Options.inc' file not found
        #include "clang/Driver/Options.inc"
                 ^~~~~~~~~~~~~~~~~

    if Options.inc wasn't generated before libclang was built
    by coincidence.

    (In the GN build, this works because lib/Driver there declares
    the dep on tablegen as a public_dep since the generated file
    is part of Driver's public interface, and then things work out
    automatically without every client of Driver having to be careful.) (detail/ViewSVN)
    by nico
  30. [Alignment] fix dubious min function alignment

    Summary:
    This was discovered while introducing the llvm::Align type.
    The original setMinFunctionAlignment used to take alignment as log2, looking at the comment it seems like instructions are to be 2-bytes aligned and not 4-bytes aligned.

    Reviewers: uweigand

    Subscribers: hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D67271 (detail/ViewSVN)
    by gchatelet
  31. [llvm-readelf] - Print unknown st_other value if present in GNU output.

    This is a fix for https://bugs.llvm.org/show_bug.cgi?id=40785.

    llvm-readelf does not print the st_value of the symbol when
    st_value has any non-visibility bits set.

    This patch:

    * Aligns "Ndx" row for the default and a new cases.
    (it was 1 space character off for the case when "PROTECTED" visibility was printed)

    * Prints "[<other>: 0x??]" for symbols which has an additional st_other bits set.
    In compare with GNU, this logic is a bit simpler and seems to be more consistent.

    For MIPS GNU can print named flags, though can't print a mix of them:
    0: 00000000 0 NOTYPE LOCAL DEFAULT UND
    1: 00000000 0 NOTYPE GLOBAL DEFAULT [OPTIONAL] UND a1
    2: 00000000 0 NOTYPE GLOBAL DEFAULT [MIPS PLT] UND a2
    3: 00000000 0 NOTYPE GLOBAL DEFAULT [MIPS PIC] UND a3
    4: 00000000 0 NOTYPE GLOBAL DEFAULT [MICROMIPS] UND a4
    5: 00000000 0 NOTYPE GLOBAL DEFAULT [MIPS16] UND a5
    6: 00000000 0 NOTYPE GLOBAL DEFAULT [<other>: c] UND b1
    7: 00000000 0 NOTYPE GLOBAL DEFAULT [<other>: 28] UND b2

    On PPC64 it can print a localentry value that is encoded in the high bits of st_other
    63: 0000000000000850 208 FUNC GLOBAL DEFAULT [<localentry>: 8] 12

    We chose to print the raw st_other field, prefixed with '0x'.

    Differential revision: https://reviews.llvm.org/D67094 (detail/ViewSVN)
    by grimar
  32. [Alignment][NFC] Use Align with TargetLowering::setMinFunctionAlignment

    Summary:
    This is patch is part of a series to introduce an Alignment type.
    See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
    See this patch for the introduction of the type: https://reviews.llvm.org/D64790

    Reviewers: courbet

    Subscribers: jyknight, sdardis, nemanjai, javed.absar, hiraditya, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, s.egerton, pzheng, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D67229 (detail/ViewSVN)
    by gchatelet
  33. [test] Update the name of the debug entry values option. NFC (detail/ViewSVN)
    by djtodoro
  34. [DFAPacketizer] Track resources for packetized instructions

    This patch allows the DFAPacketizer to be queried after a packet is formed to work out which
    resources were allocated to the packetized instructions.

    This is particularly important for targets that do their own bundle packing - it's not
    sufficient to know simply that instructions can share a packet; which slots are used is
    also required for encoding.

    This extends the emitter to emit a side-table containing resource usage diffs for each
    state transition. The packetizer maintains a set of all possible resource states in its
    current state. After packetization is complete, all remaining resource states are
    possible packetization strategies.

    The sidetable is only ~500K for Hexagon, but the extra tracking is disabled by default
    (most uses of the packetizer like MachinePipeliner don't care and don't need the extra
    maintained state).

    Differential Revision: https://reviews.llvm.org/D66936 (detail/ViewSVN)
    by jamesm
  35. [clangd] Use override keyword to override the base class method, NFC (detail/ViewSVN)
    by hokein
  36. [DebugInfo] LiveDebugValues: explicitly terminate overwritten stack locations

    If a stack spill location is overwritten by another spill instruction,
    any variable locations pointing at that slot should be terminated. We
    cannot rely on spills always being restored to registers or variable
    locations being moved by a DBG_VALUE: the register allocator is entitled
    to spill a value and then forget about it when it goes out of liveness.

    To address this, scan for memory writes to spill locations, even those we
    don't consider to be normal "spills". isSpillInstruction and
    isLocationSpill distinguish the two now. After identifying spill
    overwrites, terminate the open range, and insert a $noreg DBG_VALUE for
    that variable.

    Differential Revision: https://reviews.llvm.org/D66941 (detail/ViewSVN)
    by jmorse
  37. [AMDGPU] Mark s_barrier as having side effects but not accessing memory.

    Summary:
    This fixes poor scheduling in a function containing a barrier and a few
    load instructions.

    Without this fix, ScheduleDAGInstrs::buildSchedGraph adds an artificial
    edge in the dependency graph from the barrier instruction to the exit
    node representing live-out latency, with a latency of about 500 cycles.
    Because of this it thinks the critical path through the graph also has
    a latency of about 500 cycles. And because of that it does not think
    that any of the load instructions are on the critical path, so it
    schedules them with no regard for their (80 cycle) latency, which gives
    poor results.

    Reviewers: arsenm, dstuttard, tpr, nhaehnle

    Subscribers: kzhuravl, jvesely, wdng, yaxunl, t-tye, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D67218 (detail/ViewSVN)
    by foad
  38. gn build: Merge r371182 (detail/ViewSVN)
    by nico
  39. gn build: Merge r371179 (detail/ViewSVN)
    by nico
  40. [ARM] Fix for buildbot (detail/ViewSVN)
    by sam_parker
  41. [yaml2obj] Rename SHOffset (e_shoff) field to SHOff. NFC

    `struct Elf*_Shdr` has a field `sh_offset`, named `ShOffset` in
    llvm::ELFYAML::Section. Rename SHOffset (e_shoff) to SHOff to prevent confusion.

    Reviewed By: grimar

    Differential Revision: https://reviews.llvm.org/D67254 (detail/ViewSVN)
    by maskray
  42. Reland [LifetimeAnalysis] Support more STL idioms (template forward declaration and DependentNameType)

    Reland after https://reviews.llvm.org/D66806 fixed the false-positive diagnostics.

    Summary:
    This fixes inference of gsl::Pointer on std::set::iterator with libstdc++ (the typedef for iterator
    on the template is a DependentNameType - we can only put the gsl::Pointer attribute
    on the underlaying record after instantiation)

    inference of gsl::Pointer on std::vector::iterator with libc++ (the class was forward-declared,
    we added the gsl::Pointer on the canonical decl (the forward decl), and later when the
    template was instantiated, there was no attribute on the definition so it was not instantiated).

    and a duplicate gsl::Pointer on some class with libstdc++ (we first added an attribute to
    a incomplete instantiation, and then another was copied from the template definition
    when the instantiation was completed).

    We now add the attributes to all redeclarations to fix thos issues and make their usage easier.

    Reviewers: gribozavr

    Subscribers: Szelethus, xazax.hun, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D66179 (detail/ViewSVN)
    by mgehre
  43. [ARM] MVE Tail Predication

    The MVE and LOB extensions of Armv8.1m can be combined to enable
    'tail predication' which removes the need for a scalar remainder
    loop after vectorization. Lane predication is performed implicitly
    via a system register. The effects of predication is described in
    Section B5.6.3 of the Armv8.1-m Arch Reference Manual, the key points
    being:
    - For vector operations that perform reduction across the vector and
      produce a scalar result, whether the value is accumulated or not.
    - For non-load instructions, the predicate flags determine if the
      destination register byte is updated with the new value or if the
      previous value is preserved.
    - For vector store instructions, whether the store occurs or not.
    - For vector load instructions, whether the value that is loaded or
      whether zeros are written to that element of the destination
      register.

    This patch implements a pass that takes a hardware loop, containing
    masked vector instructions, and converts it something that resembles
    an MVE tail predicated loop. Currently, if we had code generation,
    we'd generate a loop in which the VCTP would generate the predicate
    and VPST would then setup the value of VPR.PO. The loads and stores
    would be placed in VPT blocks so this is not tail predication, but
    normal VPT predication with the predicate based upon a element
    counting induction variable. Further work needs to be done to finally
    produce a true tail predicated loop.

    Because only the loads and stores are predicated, in both the LLVM IR
    and MIR level, we will restrict support to only lane-wise operations
    (no horizontal reductions). We will perform a final check on MIR
    during loop finalisation too.

    Another restriction, specific to MVE, is that all the vector
    instructions need operate on the same number of elements. This is
    because predication is performed at the byte level and this is set
    on entry to the loop, or by the VCTP instead.

    Differential Revision: https://reviews.llvm.org/D65884 (detail/ViewSVN)
    by sam_parker
  44. [CodeGen] Do the Simple Early Return in block-placement pass to optimize the blocks

    Summary:

    Fix a bug of not update the jump table and recommit it again.

    In `block-placement` pass, it will create some patterns for unconditional we can do the simple early retrun.
    But the `early-ret` pass is before `block-placement`, we don't want to run it again.
    This patch is to do the simple early return to optimize the blocks at the last of `block-placement`.

    Reviewed By: efriedma

    Differential Revision: https://reviews.llvm.org/D63972 (detail/ViewSVN)
    by zhangkang
  45. [CMake] LLVM_COMPILE_FLAGS also applies to C files

    LLVM_COMPILE_FLAGS also applies to C files, otherwise tuning flags,
    etc. won't be picked up.

    https://reviews.llvm.org/D67171 (detail/ViewSVN)
    by davezarzycki
  46. [MIR] Change test case to read from stdin instead of file

    The

        ;CHECK: bb
        ;CHECK-NEXT: %namedVReg1353:_(p0) = COPY $d0

    parts of the test case failed when the tests were placed in a directory
    including "bb" in the path, since the full path of the file is then
    output in the
    ; ModuleID = '/repo/bb/
    line which the CHECK matched on and then the CHECK-NEXT failed. (detail/ViewSVN)
    by uabelho
  47. [X86] Add tests for extending and truncating between v16i8 and v16i64 with min-legal-vector-width=256.

    It looks like we might be able to do these in fewer steps, but
    I'm not sure. (detail/ViewSVN)
    by ctopper
  48. [X86] Prevent passing vectors of __int128 as <X x i128> in llvm IR

    As far as I can tell, gcc passes 256/512 bit vectors __int128 in memory. And passes a vector of 1 _int128 in an xmm register. The backend considers <X x i128> as an illegal type and will scalarize any arguments with that type. So we need to coerce the argument types in the frontend to match to avoid the illegal type.

    I'm restricting this to change to Linux and NetBSD based on the
    how similar ABI changes have been handled in the past.
    PS4, FreeBSD, and Darwin are unaffected. I've also added a
    new -fclang-abi-compat version to restore the old behavior.

    This issue was identified in PR42607. Though even with the types changed, we still seem to be doing some unnecessary stack realignment. (detail/ViewSVN)
    by ctopper
  49. [X86] Pre-commit vector of __int128 test cases for D64672. (detail/ViewSVN)
    by ctopper
  50. [X86] Fix bad indentation. NFC (detail/ViewSVN)
    by ctopper
  51. Fix rL371162 again (detail/ViewSVN)
    by abrachet
  52. Fix failing test from rL371162 (detail/ViewSVN)
    by abrachet
  53. [yaml2obj] Make e_phoff and e_phentsize 0 if there are no program headers

    Summary: It says [[ http://www.sco.com/developers/gabi/latest/ch4.eheader.html | here ]] that if there are no program headers than e_phoff should be 0, but currently it is always set after the header. GNU's `readelf` (but not `llvm-readelf`) complains about this: `readelf: Warning: possibly corrupt ELF header - it has a non-zero program header offset, but no program headers`.

    Reviewers: jhenderson, grimar, MaskRay, rupprecht

    Reviewed By: jhenderson, grimar, MaskRay

    Subscribers: hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D67054 (detail/ViewSVN)
    by abrachet
  54. gn build: Merge r371159 (detail/ViewSVN)
    by nico
  55. [MC] Fix undefined behavior in MCInstPrinter::formatHex

    Passing INT64_MIN to MCInstPrinter::formatHex triggers undefined
    behavior because the negation of -9223372036854775808 cannot be
    represented in type 'int64_t' (aka 'long long'). This patch puts a
    workaround in place to just print the hex value directly.

    A possible alternative involves using a small helper functions that uses
    (implementation) defined conversions to achieve the desirable value:

      static int64_t helper(int64_t V) {
        auto U = static_cast<uint64_t>(V);
        return V < 0 ? -U : U;
      }

    The underlying problem is that MCInstPrinter::formatHex(int64_t) returns
    a format_object<int64_t> and should really return a
    format_object<uint64_t>. However, that's not possible because formatImm
    needs to be able to print both as decimal (where a signed is required)
    and hex (where we'd prefer to always have an unsigned).

      format_object<int64_t> formatImm(int64_t Value) const {
        return PrintImmHex ? formatHex(Value) : formatDec(Value);
      }

    Differential revision: https://reviews.llvm.org/D67236 (detail/ViewSVN)
    by Jonas Devlieghere
  56. Cleanup test. (detail/ViewSVN)
    by asbirlea
  57. [llvm-readobj][yaml2obj] Support SHT_LLVM_SYMPART, SHT_LLVM_PART_EHDR and SHT_LLVM_PART_PHDR

    See http://lists.llvm.org/pipermail/llvm-dev/2019-February/130583.html
    and D60242 for the lld partition feature.

    This patch:

    * Teaches yaml2obj to parse the 3 section types.
    * Teaches llvm-readobj/llvm-readelf to dump the 3 section types.

    There is no test for SHT_LLVM_DEPENDENT_LIBRARIES in llvm-readobj. Add
    it as well.

    Reviewed By: thakis

    Differential Revision: https://reviews.llvm.org/D67228 (detail/ViewSVN)
    by maskray
  58. AMDGPU/GlobalISel: Avoid repeating 32-bit type lists (detail/ViewSVN)
    by arsenm
  59. AMDGPU/GlobalISel: Fix load/store of types in other address spaces

    There should probably be a size only matcher. (detail/ViewSVN)
    by arsenm
  60. GlobalISel/TableGen: Fix handling of EXTRACT_SUBREG constraints

    This was only using the correct register constraints if this was the
    final result instruction. If the extract was a sub instruction of the
    result, it would attempt to use GIR_ConstrainSelectedInstOperands on a
    COPY, which won't work. Move the handling to
    createAndImportSubInstructionRenderer so it works correctly.

    I don't fully understand why runOnPattern and
    createAndImportSubInstructionRenderer both need to handle these
    special cases, and constrain them with slightly different methods. If
    I remove the runOnPattern handling, it does break the constraint when
    the final result instruction is EXTRACT_SUBREG. (detail/ViewSVN)
    by arsenm
  61. AMDGPU: Allow getMemOperandWithOffset to analyze stack accesses

    Report soffset as a base register if the scratch resource can be
    ignored. (detail/ViewSVN)
    by arsenm
  62. AMDGPU: Fix emitting multiple stack loads for stack passed workitems

    The same stack is loaded for each workitem ID, and each use. Nothing
    prevents you from creating multiple fixed stack objects with the same
    offsets, so this was creating a load for each unique frame index,
    despite them being the same offset. Re-use the same frame index so the
    loads are CSEable. (detail/ViewSVN)
    by arsenm
  63. [AArch64] Add testcase for codegen for sdiv by 2. (detail/ViewSVN)
    by efriedma
  64. InstCombine: Fix crash on icmp of gep with addrspacecasted null (detail/ViewSVN)
    by arsenm
  65. llvm-reduce: Use %python from lit to get the correct/valid python binary for the reduction script (detail/ViewSVN)
    by dblaikie
  66. AMDGPU: Fix Register copypaste error (detail/ViewSVN)
    by arsenm
  67. [AliasSetTracker] Correct AAInfo check.

    Properly check if NewAAInfo conflicts with AAInfo.
    Update local variable and alias set that a change occured when a conflict is found.
    Resolves PR42969. (detail/ViewSVN)
    by asbirlea
  68. [SimplifyCFG] Don't SimplifyBranchOnICmpChain with ExtraCase

    Summary:
    Here we try to avoid issues with "explicit branch" with SimplifyBranchOnICmpChain
    which can check on undef. Msan by design reports branches on uninitialized
    memory and undefs, so we have false report here.

    In general msan does not like when we convert

    ```
    // If at least one of them is true we can MSAN is ok if another is undefs
    if (a || b)
      return;
    ```
    into
    ```
    // If 'a' is undef MSAN will complain even if 'b' is true
    if (a)
      return;
    if (b)
      return;
    ```

    Example

    Before optimization we had something like this:
    ```
    while (true) {
      bool maybe_undef = doStuff();

      while (true) {
        char c = getChar();
        if (c != 10 && c != 13)
         continue
        break;
      }

      // we know that c == 10 || c == 13 if we get here,
      // so msan know that branch is not affected by maybe_undef
      if (maybe_undef || c == 10 || c == 13)
        continue;
      return;
    }
    ```

    SimplifyBranchOnICmpChain will convert that into
    ```
    while (true) {
      bool maybe_undef = doStuff();

      while (true) {
        char c = getChar();
        if (c != 10 && c != 13)
          continue;
        break;
      }

      // however msan will complain here:
      if (maybe_undef)
        continue;

      // we know that c == 10 || c == 13, so either way we will get continue
      switch(c) {
        case 10: continue;
        case 13: continue;
      }
      return;
    }
    ```

    Reviewers: eugenis, efriedma

    Reviewed By: eugenis, efriedma

    Subscribers: hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D67205 (detail/ViewSVN)
    by Vitaly Buka
  69. AMDGPU: Avoid constructing new std::vector in initCandidate

    Approximately 30% of the time was spent in the std::vector
    constructor. In one testcase this pushes the scheduler to being the
    second slowest pass.

    I'm not sure I understand why these vector are necessary. The default
    scheduler initCandidate seems to use some pre-existing vectors for the
    pressure. (detail/ViewSVN)
    by arsenm
  70. gn build: Merge r371134 (detail/ViewSVN)
    by nico
  71. [Remarks] Add comparison operators to the Remark object

    and related structs.

    This also adds tests for the remarks::Remark object in general. (detail/ViewSVN)
    by thegameg
  72. Add gdb pretty printers for a wide variety of libc++ data structures (take 2).

    Summary:
    This patch is an exact duplicate of https://reviews.llvm.org/D65609, except
    that it uses the newly introduced testing framework to detect if gdb is present
    so that the tests won't fail on machines without gdb.

    Reviewers: echristo, EricWF

    Subscribers: christof, ldionne, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D67238 (detail/ViewSVN)
    by saugustine
  73. Don't assume libcxx_gdb is always set.

    libc++abi also uses this file, but doesn't use the same CMakeLists.txt. (detail/ViewSVN)
    by saugustine
  74. [ADT] Add makeArrayRef(std::array<>) template specialization (detail/ViewSVN)
    by Jan Korous
  75. [Bitstream] Add BitCodeAbbrev(std::initializer_list) constructor (detail/ViewSVN)
    by Jan Korous
  76. Docs: Update Community section on homepage

    This commit includes the following changes: Adds a Getting Involved section under Community. Moves the Development Process section under Community. Moves Sphinx Quickstart Template and How to submit an LLVM bug report from User Guides section to Getting Involved. (detail/ViewSVN)
    by dr87
  77. [libcxx] Codesign test executables if necessary

    If LLVM_CODESIGNING_IDENTITY is set, test executables need to be
    codesigned.

    Differential Revision: https://reviews.llvm.org/D66496 (detail/ViewSVN)
    by Vedant Kumar
  78. [GSYM][NFC] Fixed -Wdocumentation warning

    lib/DebugInfo/GSYM/InlineInfo.cpp:68:12: warning: parameter 'Inline' not found in the function declaration [-Wdocumentation] (detail/ViewSVN)
    by xbolva00
  79. Implement Microsoft-compatible mangling for decomposition declarations.

    Match cl.exe's mangling for decomposition declarations.

    Decomposition declarations are considered to be anonymous structs,
    and use the same convention as for anonymous struct/union declarations.

    Naming confirmed to match https://godbolt.org/z/K2osJa

    Patch from Eric Astor <epastor@google.com>!

    Differential Revision: https://reviews.llvm.org/D67202 (detail/ViewSVN)
    by nico
  80. gn build: Merge r371121 (detail/ViewSVN)
    by nico
  81. [Diagnostics] Minor improvements for -Wxor-used-as-pow

    Extracted from D66397; implemented suggestion for 2^64; tests revisited. (detail/ViewSVN)
    by xbolva00
  82. [MIR] MIRNamer pass for improving MIR test authoring experience.

    This patch reuses the MIR vreg renamer from the MIRCanonicalizerPass to cleanup
    names of vregs in a MIR file for MIR test authors. I found it useful when
    writing a regression test for a globalisel failure I encountered recently and
    thought it might be useful for other folks as well.

    Differential Revision: https://reviews.llvm.org/D67209 (detail/ViewSVN)
    by zer0
  83. Add testing infrastructure to check if gdb is available for testing.

    Reviewers: echristo, EricWF

    Subscribers: mgorny, christof, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D67194 (detail/ViewSVN)
    by saugustine
  84. gn build: Merge r371117 (detail/ViewSVN)
    by nico
  85. [clang][Index] Replace CodegenNameGenerator with ASTNameGenerator

    Follow-up to: 3ff8c3b73f6, d5d15b4c1fd

    Should be NFC since the original patch just moved the code. (detail/ViewSVN)
    by Jan Korous
  86. [globalisel][knownbits] Account for missing type constraints

    Now that we look through copies, it's possible to visit registers that
    have a register class constraint but not a type constraint. Avoid looking
    through copies when this occurs as the SrcReg won't be able to determine
    it's bit width or any known bits.

    Along the same lines, if the initial query is on a register that doesn't
    have a type constraint then the result is a default-constructed KnownBits,
    that is, a 1-bit fully-unknown value. (detail/ViewSVN)
    by dsanders
  87. [globalisel][knownbits] Correct a typo that prevented a test working as intended (detail/ViewSVN)
    by dsanders
  88. Recommit "[AArch64][GlobalISel] Teach AArch64CallLowering to handle basic sibling calls"

    Recommit basic sibling call lowering (https://reviews.llvm.org/D67189)

    The issue was that if you have a return type other than void, call lowering
    will emit COPYs to get the return value after the call.

    Disallow sibling calls other than ones that return void for now. Also
    proactively disable swifterror tail calls for now, since there's a similar issue
    with COPYs there.

    Update call-translator-tail-call.ll to include test cases for each of these
    things. (detail/ViewSVN)
    by paquette
  89. Revert: [DebugInfo] Add debug location to stubs generated by CGDeclCXX and mark them as artificial (detail/ViewSVN)
    by aganea
  90. [AST][NFC] Doc comments for ASTNameGenerator (detail/ViewSVN)
    by Jan Korous
  91. [IfConversion] Fix diamond conversion with unanalyzable branches.

    The code was incorrectly counting the number of identical instructions,
    and therefore tried to predicate an instruction which should not have
    been predicated.  This could have various effects: a compiler crash,
    an assembler failure, a miscompile, or just generating an extra,
    unnecessary instruction.

    Instead of depending on TargetInstrInfo::removeBranch, which only
    works on analyzable branches, just remove all branch instructions.

    Fixes https://bugs.llvm.org/show_bug.cgi?id=43121 and
    https://bugs.llvm.org/show_bug.cgi?id=41121 .

    Differential Revision: https://reviews.llvm.org/D67203 (detail/ViewSVN)
    by efriedma
  92. doc update: explain that Z3 is only for clang SA - thanks to LebedevRI for the suggestion (detail/ViewSVN)
    by sylvestre
  93. document the LLVM_ENABLE_Z3_SOLVER option (detail/ViewSVN)
    by sylvestre
  94. [NFC][InstCombine] Overhaul 'unsigned add overflow' tests, ensure that all 3 patterns have full test coverage (detail/ViewSVN)
    by lebedevri
  95. [X86] Enable BuildSDIVPow2 for i16.

    We're able to use a 32-bit ADD and CMOV here and should work
    well with our other i16->i32 promotion optimizations. (detail/ViewSVN)
    by ctopper
  96. [Remarks] Don't serialize metadata if a string table is not used

    For YAML remarks with no string table, the mode should not affect the
    output. (detail/ViewSVN)
    by thegameg
  97. gn build: Merge r371103 (detail/ViewSVN)
    by nico
  98. [X86] Override BuildSDIVPow2 for X86.

    As noted in PR43197, we can use test+add+cmov+sra to implement
    signed division by a power of 2.

    This is based off the similar version in AArch64, but I've
    adjusted it to use target independent nodes where AArch64 uses
    target specific CMP and CSEL nodes. I've also blocked INT_MIN
    as the transform isn't valid for that.

    I've limited this to i32 and i64 on 64-bit targets for now and only
    when CMOV is supported. i8 and i16 need further investigation to be
    sure they get promoted to i32 well.

    I adjusted a few tests to enable cmov to demonstrate the new
    codegen. I also changed twoaddr-coalesce-3.ll to 32-bit mode
    without cmov to avoid perturbing the scenario that is being
    set up there.

    Differential Revision: https://reviews.llvm.org/D67087 (detail/ViewSVN)
    by ctopper
  99. [Support] Add writeFileAtomically() to FileUtilities

    Differential Revision: https://reviews.llvm.org/D66859 (detail/ViewSVN)
    by Jan Korous
  100. gn build: (manually) merge r358706 (detail/ViewSVN)
    by nico

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 18270
originally caused by:

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Indication 1

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