Started 4 days 3 hr ago
Took 9 min 16 sec on green-dragon-09

Failed Build #5518 (Oct 11, 2019 8:52:45 PM)

Revisions
  • http://llvm.org/svn/llvm-project/llvm/trunk : 374634
  • http://llvm.org/svn/llvm-project/cfe/trunk : 374632
  • http://llvm.org/svn/llvm-project/compiler-rt/trunk : 374612
  • http://llvm.org/svn/llvm-project/debuginfo-tests/trunk : 364589
  • http://llvm.org/svn/llvm-project/libcxx/trunk : 374510
  • http://llvm.org/svn/llvm-project/clang-tools-extra/trunk : 374551
Changes
  1. recommit: [LoopVectorize][PowerPC] Estimate int and float register pressure separately in loop-vectorize

    In loop-vectorize, interleave count and vector factor depend on target register number. Currently, it does not
    estimate different register pressure for different register class separately(especially for scalar type,
    float type should not be on the same position with int type), so it's not accurate. Specifically,
    it causes too many times interleaving/unrolling, result in too many register spills in loop body and hurting performance.

    So we need classify the register classes in IR level, and importantly these are abstract register classes,
    and are not the target register class of backend provided in td file. It's used to establish the mapping between
    the types of IR values and the number of simultaneous live ranges to which we'd like to limit for some set of those types.

    For example, POWER target, register num is special when VSX is enabled. When VSX is enabled, the number of int scalar register is 32(GPR),
    float is 64(VSR), but for int and float vector register both are 64(VSR). So there should be 2 kinds of register class when vsx is enabled,
    and 3 kinds of register class when VSX is NOT enabled.

    It runs on POWER target, it makes big(+~30%) performance improvement in one specific bmk(503.bwaves_r) of spec2017 and no other obvious degressions.

    Differential revision: https://reviews.llvm.org/D67148 (detail/ViewSVN)
    by wuzish
  2. [clang][IFS] Updating tests to pass on -fvisibility=hidden builds (NFCi).

    Special thanks to JamesNagurne who got to the bottom of this; landing this on
    his behalf.

    Differential Revision: https://reviews.llvm.org/D68897 (detail/ViewSVN)
    by zer0

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 18487
originally caused by:

This run spent:

  • 6.7 sec waiting;
  • 9 min 16 sec build duration;
  • 9 min 23 sec total from scheduled to completion.

Identified problems

Ninja target failed

Below is a link to the first failed ninja target.
Indication 1

Compile Error

This build failed because of a compile error. Below is a list of all errors in the build log:
Indication 2

Missing test results

The test result file Jenkins is looking for does not exist after the build.
Indication 3