Started 1 yr 5 mo ago
Took 37 min on green-dragon-23

Failed Build #2 (Nov 30, 2018 3:51:41 PM)

  • : 348052
  • : 348053
  • : 348040
  • : 347930
  1. Revert "Revert r347417 "Re-Reinstate 347294 with a fix for the failures.""

    It seems the two failing tests can be simply fixed after r348037

    Fix 3 cases in Analysis/builtin-functions.cpp
    Delete the bad CodeGen/builtin-constant-p.c for now (detail)
    by maskray
  2. [codeview] Remove dead macros for codeview record serialization, NFC

    These weren't needed when we went to the yaml IO style of serialization,
    which has "mapOptional". (detail)
    by rnk
  3. LegacyDivergenceAnalysis: fix uninitialized value

    Change-Id: I014502e431a68f7beddf169f6a3d19dac5dd2c26 (detail)
    by nha
  4. AMDGPU: Divergence-driven selection of scalar buffer load intrinsics

    Moving SMRD to VMEM in SIFixSGPRCopies is rather bad for performance if
    the load is really uniform. So select the scalar load intrinsics directly
    to either VMEM or SMRD buffer loads based on divergence analysis.

    If an offset happens to end up in a VGPR -- either because a floating
    point calculation was involved, or due to other remaining deficiencies
    in SIFixSGPRCopies -- we use v_readfirstlane.

    There is some unrelated churn in tests since we now select MUBUF offsets
    in a unified way with non-scalar buffer loads.

    Change-Id: I170e6816323beb1348677b358c9d380865cd1a19

    Reviewers: arsenm, alex-t, rampitec, tpr

    Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, t-tye, llvm-commits

    Differential Revision: (detail)
    by nha
  5. AMDGPU: Fix various issues around the VirtReg2Value mapping

    The VirtReg2Value mapping is crucial for getting consistently
    reliable divergence information into the SelectionDAG. This
    patch fixes a bunch of issues that lead to incorrect divergence
    info and introduces tight assertions to ensure we don't regress:

    1. VirtReg2Value is generated lazily; there were some cases where
       a lookup was performed before all relevant virtual registers were
       created, leading to an out-of-sync mapping. Those cases were:

      - Complex code to lower formal arguments that generated CopyFromReg
        nodes from live-in registers (fixed by never querying the mapping
        for live-in registers).

      - Code that generates CopyToReg for formal arguments that are used
        outside the entry basic block (fixed by never querying the
        mapping for Register nodes, which don't need the divergence info

    2. For complex values that are lowered to a sequence of registers,
       all registers must be reflected in the VirtReg2Value mapping.

    I am not adding any new tests, since I'm not actually aware of any
    bugs that these problems are causing with trunk as-is. However,
    I recently added a test case (in r346423) which fails when D53283 is
    applied without this change. Also, the new assertions should provide
    most of the effective test coverage.

    There is one test change in sdwa-peephole.ll. The underlying issue
    is that since the divergence info is now correct, the DAGISel will
    select V_OR_B32 directly instead of S_OR_B32. This leads to an extra
    COPY which affects the behavior of MachineLICM in a way that ends up
    with the S_MOV_B32 with the constant in a different basic block than
    the V_OR_B32, which is presumably what defeats the peephole.

    Reviewers: alex-t, arsenm, rampitec

    Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

    Differential Revision: (detail)
    by nha
  6. [DA] GPUDivergenceAnalysis for unstructured GPU kernels

    This is patch #3 of the new DivergenceAnalysis


    The GPUDivergenceAnalysis is intended to eventually supersede the existing
    LegacyDivergenceAnalysis. The existing LegacyDivergenceAnalysis produces
    incorrect results on unstructured Control-Flow Graphs:


    This patch adds the option -use-gpu-divergence-analysis to the
    LegacyDivergenceAnalysis to turn it into a transparent wrapper for the

    Reviewers: nhaehnle

    Reviewed By: nhaehnle

    Subscribers: jholewinski, jvesely, jfb, llvm-commits, alex-t, sameerds, arsenm, nhaehnle

    Differential Revision: (detail)
    by nha
  7. [x86] add tests for undef + partial undef constant folding; NFC

    Keep this file sync'd with the instsimplify version (rL348045). (detail)
    by spatel
  8. [X86] Split skylake-avx512 run lines in SLP vectorizer tests to cover -mprefer=vector-width=256 and -mprefer-vector-width=512.

    This will make these tests immune if we ever change the default behavior of -march=skylake-avx512 to prefer 256 bit vectors. (detail)
    by ctopper
  9. [InstSimplify] add tests for undef + partial undef constant folding; NFC

    These tests should probably go under a separate test file because they
    should fold with just -constprop, but they're similar to the scalar
    tests already in here. (detail)
    by spatel

Started by timer (4 times)

This run spent:

  • 57 min waiting;
  • 37 min build duration;
  • 1 hr 35 min total from scheduled to completion.
Test Result (675 failures )Show all failed tests >>>

Identified problems

Regression test failed

This build failed because a regression test in the test suite FAILed. See the test report for details.
Indication 1

Ninja target failed

Below is a link to the first failed ninja target.
Indication 2