FailedChanges

Summary

  1. [ARM] LE support in ConstantIslands (details)
  2. [AMDGPU]: PHI Elimination hooks added for custom COPY insertion. Fixed (details)
  3. [llvm-readobj] - Fix a TODO in elf-reloc-zero-name-or-value.test. (details)
  4. [llvm-ar] Parse 'h' and '-h': display help and exit (details)
  5. [llvm-readobj] - Fix BB after r372087. (details)
  6. [lldb] [Process/gdb-remote] Fix defaulting signal to invalid in action (details)
  7. [SimplifyLibCalls] Mark known arguments with nonnull (details)
  8. Patch from Phabricator (details)
  9. [NFC} Updated test (details)
  10. [ELF][AARCH64] Refactor AArchErrataFix to match changes in ARMErrataFix (details)
  11. [NFC] Updated test (details)
  12. [SimplifyLibCalls] Fix -Wunused-result after D53342/r372091 (details)
  13. [NFCI] Fixed buildbots (details)
  14. [InstCombine] Annotate strdup with deref_or_null (details)
  15. [SVE][MVT] Fixed-length vector MVT ranges (details)
  16. [SLC] Preserve attrs for strncpy(x, "", y) -> memset(align 1 x, '\0', y) (details)
  17. Add SemanticRanges to Clangd server. (details)
  18. [X86] Use APInt::getLowBitsSet helper. NFCI. (details)
  19. Revert Patch from Phabricator (details)
  20. [Attributor][Fix] Initialize the cache prior to using it (details)
  21. [RISCV] Switch to the Machine Scheduler (details)
  22. [docs] Make --version text more correct (details)
  23. [yaml2obj/obj2yaml] - Allow setting an arbitrary values for e_machine. (details)
  24. [obj2yaml] - Support PPC64 relocation types. (details)
  25. [llvm-readobj] - Test PPC64 relocations properly. (details)
  26. [ARM][LowOverheadLoops] Add LR def safety check (details)
  27. lldb: move a test input to the test Inputs dir (details)
  28. Hide implementation details in namespaces. (details)
  29. [ARM] Fix for MVE load/store stack accesses (details)
  30. [LoopVectorize] Don't dereference a dyn_cast result. NFCI. (details)
  31. InterleavedAccessInfo - Don't dereference a dyn_cast result. NFCI. (details)
  32. [X86] X86DAGToDAGISel::tryFoldLoad - assert root/parent pointers are (details)
  33. [OpenCL] Tidy up some comments; NFC (details)
  34. [RISCV][NFC] Use NoRegister instead of 0 literal (details)
  35. [ARM] Fix for buildbots (details)
  36. [llvm-readobj/llvm-objdump] - Improve how tool locate the dynamic table (details)
  37. gn build: (manually) merge r372076 (details)
  38. Add SpellingNotCalculated to Attribute Enums to suppress UBSan warnings (details)
  39. Revert "[SLC] Preserve attrs for strncpy(x, "", y) -> memset(align 1 x, (details)
  40. [ARM] Fix for buildbots (details)
  41. [RISCV] Unbreak the build (details)
  42. [clangd] Fix another TSAN issue (details)
  43. [clang-format] Fix cleanup of `AnnotatedLine` to include children nodes. (details)
  44. [OPENMP]Try to rework the test to pacify the buildbots, NFC. (details)
  45. [ARM] Reserve an emergency spill slot for fp16 addressing modes that (details)
  46. [ARM] Fixup pipeline test. NFC (details)
  47. [ARM] Add a SelectTAddrModeImm7 for MVE narrow loads and stores (details)
  48. GSYM: add encoding and decoding to FunctionInfo (details)
  49. Move DK_Misexpect for compatability with (details)
  50. [MemorySSA] Update MSSA for non-conventional AA. (details)
  51. [MemorySSA] Fix phi insertion when inserting a def. (details)
  52. [PowerPC] Exploit single instruction load-and-splat for word and (details)
  53. [ASAN] Adjust asan tests due to new optimizations (details)
  54. Reland "[SLC] Preserve attrs for strncpy(x, "", y) -> memset(align 1 x, (details)
Commit 95b28a4c728adfebd30406d88151fb0df51a6c5b by sam.parker
[ARM] LE support in ConstantIslands
The low-overhead branch extension provides a loop-end 'LE' instruction
that performs no decrement nor compare, it just jumps backwards. This
patch modifies the constant islands pass to try to insert LE
instructions in place of a Thumb2 conditional branch, instead of
shrinking it. This only happens if a cmp can be converted to a cbn/z and
used to exit the loop.
Differential Revision: https://reviews.llvm.org/D67404
llvm-svn: 372085
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-reorder.mir
The file was modifiedllvm/lib/Target/ARM/ARMConstantIslandPass.cpp
The file was modifiedllvm/test/CodeGen/ARM/O3-pipeline.ll
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-le-simple.ll
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec.mir
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-cbnz.mir
Commit 6524a7a2b9ca072bd7f7b4355d1230e70c679d2f by Alexander.Timofeev
[AMDGPU]: PHI Elimination hooks added for custom COPY insertion. Fixed
Defferential Revision: https://reviews.llvm.org/D67101
Reviewers: rampitec, vpykhtin llvm-svn: 372086
The file was modifiedllvm/test/CodeGen/AMDGPU/phi-elimination-assertion.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetInstrInfo.h
The file was modifiedllvm/lib/CodeGen/PHIElimination.cpp
The file was addedllvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.h
Commit de1bef0b1b2d111e07450686843dec76e2763130 by grimar
[llvm-readobj] - Fix a TODO in elf-reloc-zero-name-or-value.test.
The "TODO" mentioned was:
"Add test for symbol with no name but with a value once yaml2obj allows
referencing symbols with no name from relocations."
We can do it now.
Differential revision: https://reviews.llvm.org/D67609
llvm-svn: 372087
The file was modifiedllvm/test/tools/llvm-readobj/elf-reloc-zero-name-or-value.test
Commit 1ecba6f8efd2bdc466b4811081573186abd9a975 by maskray
[llvm-ar] Parse 'h' and '-h': display help and exit
Support `llvm-ar h` and `llvm-ar -h` because they may be what users try
at first. Note, operation 'h' is undocumented in GNU ar.
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D67560
llvm-svn: 372088
The file was modifiedllvm/tools/llvm-ar/llvm-ar.cpp
The file was addedllvm/test/tools/llvm-ar/help-message.test
Commit 48de660bbf0d824df77402c8856320fe534c2615 by grimar
[llvm-readobj] - Fix BB after r372087.
Seems I forgot to update the number of bytes checked.
llvm-svn: 372089
The file was modifiedllvm/test/tools/llvm-readobj/elf-reloc-zero-name-or-value.test
Commit e4d25e9e16278d7926ec43c6ea7571e869d0a619 by mgorny
[lldb] [Process/gdb-remote] Fix defaulting signal to invalid in action
list
Fix processing of "C" packet with signal for the whole process to
default signal value for action list to LLDB_INVALID_SIGNAL_NUMBER
rather than 0.
Differential Revision: https://reviews.llvm.org/D67625
llvm-svn: 372090
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
Commit e80fcf03407acd6429d07e4a45185ac546ffa37c by david.bolvansky
[SimplifyLibCalls] Mark known arguments with nonnull
Reviewers: efriedma, jdoerfert
Reviewed By: jdoerfert
Subscribers: ychen, rsmith, joerg, aaron.ballman, lebedev.ri, uenoku,
jdoerfert, hfinkel, javed.absar, spatel, dmgreen, llvm-commits
Differential Revision: https://reviews.llvm.org/D53342
llvm-svn: 372091
The file was modifiedllvm/test/Analysis/BasicAA/gep-alias.ll
The file was modifiedllvm/test/Transforms/InstCombine/strncpy_chk-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/memmove_chk-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/puts-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/strncpy-2.ll
The file was modifiedllvm/test/Transforms/InstCombine/memcmp-constant-fold.ll
The file was modifiedllvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h
The file was modifiedllvm/test/Transforms/InstCombine/strcpy_chk-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/ARM/strcmp.ll
The file was modifiedllvm/test/Transforms/InstCombine/memset_chk-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/fortify-folding.ll
The file was modifiedllvm/test/Transforms/InstCombine/memcpy_chk-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/strcmp-memcmp.ll
The file was modifiedllvm/test/Transforms/InstCombine/strncat-3.ll
The file was modifiedllvm/test/Analysis/TypeBasedAliasAnalysis/memcpyopt.ll
The file was modifiedllvm/test/Transforms/InstCombine/strcpy-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/memcpy-to-load.ll
The file was modifiedllvm/test/Transforms/InstCombine/mem-deref-bytes-addrspaces.ll
The file was modifiedllvm/test/Transforms/InstCombine/printf-2.ll
The file was modifiedllvm/test/Transforms/InstCombine/sprintf-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/getelementptr.ll
The file was modifiedllvm/test/Transforms/InstCombine/strncat-2.ll
The file was modifiedllvm/test/Transforms/InstCombine/stpcpy_chk-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/memcpy-from-global.ll
The file was addedllvm/test/Transforms/InstCombine/memrchr.ll
The file was modifiedllvm/test/Transforms/InstCombine/snprintf.ll
The file was modifiedllvm/test/Transforms/InstCombine/strncmp-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/strrchr-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/malloc-free-delete.ll
The file was modifiedllvm/test/Transforms/InstCombine/memcpy.ll
The file was modifiedllvm/test/Transforms/InstCombine/strchr-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/strcmp-1.ll
The file was modifiedllvm/test/Other/cgscc-libcall-update.ll
The file was modifiedllvm/test/Transforms/InstCombine/printf-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/stpcpy-1.ll
The file was modifiedllvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
The file was modifiedllvm/test/CodeGen/X86/no-plt-libcalls.ll
The file was modifiedllvm/test/Transforms/InstCombine/mempcpy.ll
The file was modifiedllvm/test/Transforms/InstCombine/strncpy-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/strlen-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/strstr-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/memchr.ll
The file was modifiedllvm/test/Transforms/InstCombine/strpbrk-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/memset-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/mem-deref-bytes.ll
The file was modifiedllvm/test/Transforms/InstCombine/strcspn-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/strncmp-2.ll
The file was modifiedllvm/test/Transforms/InstCombine/objsize.ll
The file was modifiedllvm/test/Transforms/InstCombine/align-addr.ll
Commit e38695a0255c9e7b53639f349f8101bae1ce5c04 by luismarques
Patch from Phabricator
llvm-svn: 372092
The file was modifiedllvm/test/CodeGen/RISCV/bare-select.ll
The file was modifiedllvm/test/CodeGen/RISCV/arith-with-overflow.ll
The file was modifiedllvm/test/CodeGen/RISCV/lsr-legaladdimm.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVSubtarget.h
The file was modifiedllvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-previous-failure.ll
The file was modifiedllvm/test/CodeGen/RISCV/select-optimize-multiple.ll
The file was modifiedllvm/test/CodeGen/RISCV/alu64.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
The file was modifiedllvm/test/CodeGen/RISCV/atomic-rmw.ll
The file was modifiedllvm/test/CodeGen/RISCV/codemodel-lowering.ll
The file was modifiedllvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
The file was modifiedllvm/test/CodeGen/RISCV/blockaddress.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
The file was modifiedllvm/test/CodeGen/RISCV/mem.ll
The file was modifiedllvm/test/CodeGen/RISCV/imm-cse.ll
The file was modifiedllvm/test/CodeGen/RISCV/mul.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
The file was modifiedllvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
The file was modifiedllvm/test/CodeGen/RISCV/imm.ll
The file was modifiedllvm/test/CodeGen/RISCV/mem64.ll
The file was modifiedllvm/test/CodeGen/RISCV/vararg.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
The file was modifiedllvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-br-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/setcc-logic.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll
The file was modifiedllvm/test/CodeGen/RISCV/fp128.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
The file was modifiedllvm/test/CodeGen/RISCV/shifts.ll
The file was modifiedllvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
The file was modifiedllvm/test/CodeGen/RISCV/addcarry.ll
The file was modifiedllvm/test/CodeGen/RISCV/callee-saved-gprs.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-intrinsics.ll
The file was modifiedllvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/div.ll
The file was modifiedllvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
The file was modifiedllvm/test/CodeGen/RISCV/add-before-shl.ll
The file was modifiedllvm/test/CodeGen/RISCV/get-setcc-result-type.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-imm.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-select-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/remat.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-intrinsics.ll
The file was modifiedllvm/test/CodeGen/RISCV/legalize-fneg.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-arith.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-arith.ll
The file was modifiedllvm/test/CodeGen/RISCV/indirectbr.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-calling-conv.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64f-float-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-br-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-mem.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
The file was modifiedllvm/test/CodeGen/RISCV/frame-info.ll
The file was modifiedllvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-lp64.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-mem.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-select-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-imm.ll
The file was modifiedllvm/test/CodeGen/RISCV/alloca.ll
The file was modifiedllvm/test/CodeGen/RISCV/compress.ll
The file was modifiedllvm/test/CodeGen/RISCV/atomic-cmpxchg-flag.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64i-complex-float.ll
The file was modifiedllvm/test/CodeGen/RISCV/split-offsets.ll
Commit 3d33e97be638bb8e91481decb1da07d8123ec17f by david.bolvansky
[NFC} Updated test
llvm-svn: 372093
The file was modifiedllvm/test/Transforms/CodeGenPrepare/X86/memset_chk-simplify-nobuiltin.ll
Commit 43d32cdd8717c3a6c35bd47d1e32789c854e6955 by peter.smith
[ELF][AARCH64] Refactor AArchErrataFix to match changes in ARMErrataFix
NFC.
D67284 introduced ARMErrataFix.cpp which was derived from
AArch64ErrataFix.cpp. There were some useful refactoring changes made to
ARMErrataFix.cpp made as part of the review. This change applies the
relevant changes back to AArch64ErrataFix.cpp.
Main changes are:
- Old style variable names in comments like IS, are now new style isec.
- Simplify init() collection of mappingSymbols to always start with a
code mapping symbol.
- Simplify logic in mergeCmp().
- Fix one 80 column overflow caused by IS -> isec transformation.
Differential Revision: https://reviews.llvm.org/D67622
llvm-svn: 372094
The file was modifiedlld/ELF/AArch64ErrataFix.cpp
Commit 957b9cdd2692178b9635cbbbcb94e78a5bc24473 by david.bolvansky
[NFC] Updated test
llvm-svn: 372095
The file was modifiedclang/test/CodeGen/tbaa-struct.cpp
Commit 83517637095060bc045a879caeecd2f2d8ea0e1f by maskray
[SimplifyLibCalls] Fix -Wunused-result after D53342/r372091
llvm-svn: 372096
The file was modifiedllvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
Commit 3a3dddd9d72edecc774efaee153e876fe74fed6c by david.bolvansky
[NFCI] Fixed buildbots
llvm-svn: 372097
The file was modifiedllvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
Commit be2487a2ba43f3929c894e8cf8fe3ddb0b9c6a24 by david.bolvansky
[InstCombine] Annotate strdup with deref_or_null
llvm-svn: 372098
The file was modifiedllvm/lib/Analysis/MemoryBuiltins.cpp
The file was modifiedllvm/include/llvm/Analysis/MemoryBuiltins.h
The file was modifiedllvm/test/Transforms/InstCombine/deref-alloc-fns.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was modifiedllvm/test/Transforms/InstCombine/objsize.ll
Commit 1a9195d817d35a0464394018a3575ccfe49eda80 by graham.hunter
[SVE][MVT] Fixed-length vector MVT ranges
  * Reordered MVT simple types to group scalable vector types
   together.
* New range functions in MachineValueType.h to only iterate over
   the fixed-length int/fp vector types.
* Stopped backends which don't support scalable vector types from
   iterating over scalable types.
Reviewers: sdesmalen, greened
Reviewed By: greened
Differential Revision: https://reviews.llvm.org/D66339
llvm-svn: 372099
The file was modifiedllvm/lib/Target/Mips/MipsISelLowering.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonSubtarget.h
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLowering.cpp
The file was modifiedllvm/include/llvm/Support/MachineValueType.h
The file was modifiedllvm/lib/CodeGen/TargetLoweringBase.cpp
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/lib/Target/Sparc/SparcISelLowering.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/utils/TableGen/CodeGenDAGPatterns.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/ValueTypes.td
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
The file was modifiedllvm/lib/Target/Mips/MipsSEISelLowering.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit ded48e93e600345159a826636c686ca481a3da69 by david.bolvansky
[SLC] Preserve attrs for strncpy(x, "", y) -> memset(align 1 x, '\0', y)
llvm-svn: 372101
The file was modifiedllvm/test/Transforms/InstCombine/strncpy-1.ll
The file was modifiedllvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
Commit 79d19bdf8196a2b5b8e9c875df8a7625443bf41d by usx
Add SemanticRanges to Clangd server.
Summary: Adds Semantic Ranges capabilities to Clangd server. Also adds
tests for running it via clangd server.
This differs from the LSP spec as the spec needs this to be evaluated on
multiple 'pos' and the expected output is an list of list of semantic
ranges. This is majorly for multi cursor and assuming this is a rare
thing, we don't want to optimize make things complicated just for this.
This should be done in the LSP level by queueing one request per 'pos'
in the input.
LSP Spec:
https://github.com/microsoft/language-server-protocol/blob/dbaeumer/3.15/specification.md#textDocument_selectionRange
Reviewers: hokein
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet,
cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D67650
llvm-svn: 372102
The file was modifiedclang-tools-extra/clangd/unittests/SyncAPI.h
The file was modifiedclang-tools-extra/clangd/unittests/SemanticSelectionTests.cpp
The file was modifiedclang-tools-extra/clangd/unittests/SyncAPI.cpp
The file was modifiedclang-tools-extra/clangd/ClangdServer.cpp
The file was modifiedclang-tools-extra/clangd/ClangdServer.h
Commit 0b10da7cc786b36b8bf553222ac27a4170770110 by llvm-dev
[X86] Use APInt::getLowBitsSet helper. NFCI.
Also avoids a static analyzer warning about out of range shifts.
llvm-svn: 372103
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 2d550d19b321837aac647ec9e8c5b6f26f682b17 by luismarques
Revert Patch from Phabricator
This reverts r372092 (git commit
e38695a0255c9e7b53639f349f8101bae1ce5c04)
llvm-svn: 372104
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/legalize-fneg.ll
The file was modifiedllvm/test/CodeGen/RISCV/alu64.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/frame-info.ll
The file was modifiedllvm/test/CodeGen/RISCV/imm.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64i-complex-float.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVSubtarget.h
The file was modifiedllvm/test/CodeGen/RISCV/double-calling-conv.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/indirectbr.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-arith.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-select-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-previous-failure.ll
The file was modifiedllvm/test/CodeGen/RISCV/compress.ll
The file was modifiedllvm/test/CodeGen/RISCV/atomic-rmw.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64f-float-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
The file was modifiedllvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll
The file was modifiedllvm/test/CodeGen/RISCV/get-setcc-result-type.ll
The file was modifiedllvm/test/CodeGen/RISCV/vararg.ll
The file was modifiedllvm/test/CodeGen/RISCV/mem64.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-intrinsics.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-lp64.ll
The file was modifiedllvm/test/CodeGen/RISCV/shifts.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-imm.ll
The file was modifiedllvm/test/CodeGen/RISCV/fp128.ll
The file was modifiedllvm/test/CodeGen/RISCV/split-offsets.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
The file was modifiedllvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-intrinsics.ll
The file was modifiedllvm/test/CodeGen/RISCV/remat.ll
The file was modifiedllvm/test/CodeGen/RISCV/select-optimize-multiple.ll
The file was modifiedllvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
The file was modifiedllvm/test/CodeGen/RISCV/atomic-cmpxchg-flag.ll
The file was modifiedllvm/test/CodeGen/RISCV/bare-select.ll
The file was modifiedllvm/test/CodeGen/RISCV/lsr-legaladdimm.ll
The file was modifiedllvm/test/CodeGen/RISCV/mul.ll
The file was modifiedllvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
The file was modifiedllvm/test/CodeGen/RISCV/add-before-shl.ll
The file was modifiedllvm/test/CodeGen/RISCV/blockaddress.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-br-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-br-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/imm-cse.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-mem.ll
The file was modifiedllvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
The file was modifiedllvm/test/CodeGen/RISCV/codemodel-lowering.ll
The file was modifiedllvm/test/CodeGen/RISCV/setcc-logic.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-mem.ll
The file was modifiedllvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
The file was modifiedllvm/test/CodeGen/RISCV/arith-with-overflow.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
The file was modifiedllvm/test/CodeGen/RISCV/addcarry.ll
The file was modifiedllvm/test/CodeGen/RISCV/callee-saved-gprs.ll
The file was modifiedllvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-imm.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-arith.ll
The file was modifiedllvm/test/CodeGen/RISCV/div.ll
The file was modifiedllvm/test/CodeGen/RISCV/mem.ll
The file was modifiedllvm/test/CodeGen/RISCV/alloca.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-select-fcmp.ll
Commit 3ab9e8b81858cdcf4f381b4238315cb1d434e984 by jdoerfert
[Attributor][Fix] Initialize the cache prior to using it
Summary: There were segfaults as we modified and iterated the
instruction maps in the cache at the same time. This was happening
because we created new instructions while we populated the cache. This
fix changes the order in which we perform these actions. First, the
caches for the whole module are created, then we start to create
abstract attributes.
I don't have a unit test but the LLVM test suite exposes this problem.
Reviewers: uenoku, sstefan1
Subscribers: hiraditya, bollu, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67232
llvm-svn: 372105
The file was modifiedllvm/test/Transforms/FunctionAttrs/fn_noreturn.ll
The file was modifiedllvm/test/Transforms/FunctionAttrs/nounwind.ll
The file was modifiedllvm/test/Transforms/FunctionAttrs/arg_returned.ll
The file was modifiedllvm/test/Transforms/FunctionAttrs/dereferenceable.ll
The file was modifiedllvm/test/Transforms/FunctionAttrs/liveness.ll
The file was modifiedllvm/test/Transforms/FunctionAttrs/noreturn_async.ll
The file was modifiedllvm/test/Transforms/FunctionAttrs/noalias_returned.ll
The file was modifiedllvm/include/llvm/Transforms/IPO/Attributor.h
The file was modifiedllvm/test/Transforms/FunctionAttrs/willreturn.ll
The file was modifiedllvm/test/Transforms/FunctionAttrs/nofree-attributor.ll
The file was modifiedllvm/test/Transforms/FunctionAttrs/nosync.ll
The file was modifiedllvm/lib/Transforms/IPO/Attributor.cpp
The file was modifiedllvm/test/Transforms/FunctionAttrs/noreturn_sync.ll
The file was modifiedllvm/test/Transforms/FunctionAttrs/internal-noalias.ll
The file was modifiedllvm/test/Transforms/FunctionAttrs/align.ll
Commit 3d0fbafd0bce43bb9106230a45d1130f7a40e5ec by luismarques
[RISCV] Switch to the Machine Scheduler
Most of the test changes are trivial instruction reorderings and
differing register allocations, without any obvious performance impact.
Differential Revision: https://reviews.llvm.org/D66973
llvm-svn: 372106
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-calling-conv.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-arith.ll
The file was modifiedllvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-imm.ll
The file was modifiedllvm/test/CodeGen/RISCV/imm-cse.ll
The file was modifiedllvm/test/CodeGen/RISCV/legalize-fneg.ll
The file was modifiedllvm/test/CodeGen/RISCV/alu64.ll
The file was modifiedllvm/test/CodeGen/RISCV/alloca.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64f-float-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
The file was modifiedllvm/test/CodeGen/RISCV/split-offsets.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
The file was modifiedllvm/test/CodeGen/RISCV/codemodel-lowering.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-intrinsics.ll
The file was modifiedllvm/test/CodeGen/RISCV/atomic-cmpxchg-flag.ll
The file was modifiedllvm/test/CodeGen/RISCV/mem64.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-intrinsics.ll
The file was modifiedllvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
The file was modifiedllvm/test/CodeGen/RISCV/indirectbr.ll
The file was modifiedllvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
The file was modifiedllvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/frame-info.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64i-complex-float.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
The file was modifiedllvm/test/CodeGen/RISCV/blockaddress.ll
The file was modifiedllvm/test/CodeGen/RISCV/div.ll
The file was modifiedllvm/test/CodeGen/RISCV/shifts.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/setcc-logic.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-arith.ll
The file was modifiedllvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll
The file was modifiedllvm/test/CodeGen/RISCV/addcarry.ll
The file was modifiedllvm/test/CodeGen/RISCV/remat.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/vararg.ll
The file was modifiedllvm/test/CodeGen/RISCV/arith-with-overflow.ll
The file was modifiedllvm/test/CodeGen/RISCV/fp128.ll
The file was modifiedllvm/test/CodeGen/RISCV/select-optimize-multiple.ll
The file was modifiedllvm/test/CodeGen/RISCV/callee-saved-gprs.ll
The file was modifiedllvm/test/CodeGen/RISCV/lsr-legaladdimm.ll
The file was modifiedllvm/test/CodeGen/RISCV/mem.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-previous-failure.ll
The file was modifiedllvm/test/CodeGen/RISCV/imm.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/bare-select.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/compress.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVSubtarget.h
The file was modifiedllvm/test/CodeGen/RISCV/add-before-shl.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
The file was modifiedllvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
The file was modifiedllvm/test/CodeGen/RISCV/get-setcc-result-type.ll
The file was modifiedllvm/test/CodeGen/RISCV/mul.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-br-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-mem.ll
The file was modifiedllvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-mem.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-select-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
The file was modifiedllvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
The file was modifiedllvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-br-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-imm.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-lp64.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-select-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/atomic-rmw.ll
Commit 778a5e57349e78b0fb7dbacd131d92b98ad0e92e by jh7370
[docs] Make --version text more correct
Follow-up to r371983. Referring to "this program" in the description of
the --version option in the documentation isn't exactly correct, because
the docs are not part of the program, and so "this program" doesn't
really refer to anything. This patch brings the other users of this
terminology into line with the new updates to llvm-size and
llvm-strings.
Reviewed by: alexshap, MaskRay
Differential Revision: https://reviews.llvm.org/D67618
llvm-svn: 372107
The file was modifiedllvm/docs/CommandGuide/llvm-nm.rst
The file was modifiedllvm/docs/CommandGuide/llvm-cxxfilt.rst
The file was modifiedllvm/docs/CommandGuide/llvm-readelf.rst
The file was modifiedllvm/docs/CommandGuide/llvm-objcopy.rst
The file was modifiedllvm/docs/CommandGuide/llvm-readobj.rst
The file was modifiedllvm/docs/CommandGuide/llvm-objdump.rst
The file was modifiedllvm/docs/CommandGuide/llvm-strip.rst
Commit cfc0ba3852cac41f4881689a953a03487896c8f6 by grimar
[yaml2obj/obj2yaml] - Allow setting an arbitrary values for e_machine.
Currently we only allow using a known named constants for `Machine`
field in YAML documents.
This patch allows using any numbers (valid or "unknown") and adds test
cases for current and new functionality.
With this it is possible to write a test cases for really unknown EM_*
targets.
Differential revision: https://reviews.llvm.org/D67652
llvm-svn: 372108
The file was modifiedllvm/lib/ObjectYAML/ELFYAML.cpp
The file was addedllvm/test/tools/obj2yaml/elf-emachine.yaml
The file was addedllvm/test/tools/yaml2obj/elf-emachine.yaml
Commit 82d83733dd70b574ef9e3bff70fd5c1012988867 by grimar
[obj2yaml] - Support PPC64 relocation types.
We do not support them and fail with llvm_unreachable currently. This is
not the only target we do not support and also seems we are missing the
tests for those we have already. But I needed this one for another
patch, so posted it separatelly.
Relocation names are taken from
llvm\include\llvm\BinaryFormat\ELFRelocs\PowerPC64.def
Differential revision: https://reviews.llvm.org/D67615
llvm-svn: 372109
The file was addedllvm/test/tools/obj2yaml/elf-ppc64-relocations.yaml
The file was modifiedllvm/lib/ObjectYAML/ELFYAML.cpp
Commit 589293800afa6238c44539dfda865e4dd418dec3 by grimar
[llvm-readobj] - Test PPC64 relocations properly.
We had a precompiled binary committed and not all of the relocations
supported were tested. This patch fixes this.
Differential revision: https://reviews.llvm.org/D67617
llvm-svn: 372110
The file was modifiedllvm/test/tools/llvm-readobj/reloc-types-elf-ppc64.test
The file was removedllvm/test/tools/llvm-readobj/Inputs/relocs.obj.elf-ppc64
Commit 36c922278e6e7fb2083dc29dda950dfac73a194c by sam.parker
[ARM][LowOverheadLoops] Add LR def safety check
Converting the *LoopStart pseudo instructions into DLS/WLS results in LR
being defined. These instructions were inserted on the assumption that
LR would already contain the loop counter because a mov is introduced
during ISel as the the consumers in the loop can only use LR. That
assumption proved wrong!
So perform a safety check, finding an appropriate place to insert the
DLS/WLS instructions or revert if this isn't possible.
Differential Revision: https://reviews.llvm.org/D67539
llvm-svn: 372111
The file was modifiedllvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-liveout.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-write.mir
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-read.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir
The file was removedllvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-spill.mir
Commit 88b4b9f97391e8beec02fe1f0a4d16e1b0e12610 by krasimir
lldb: move a test input to the test Inputs dir
Summary: This makes the input file for a new test added in r372060
directly available in the Inputs subdirectory of the test dir.
Differential Revision: https://reviews.llvm.org/D67655
llvm-svn: 372112
The file was modifiedlldb/lit/Commands/command-script-import.test
The file was addedlldb/lit/Commands/Inputs/main.c
Commit df4b9a3f4f7acf76968540391223ec23844e6aa7 by benny.kra
Hide implementation details in namespaces.
llvm-svn: 372113
The file was modifiedclang/lib/Sema/SemaLookup.cpp
The file was modifiedllvm/lib/Target/X86/X86FrameLowering.cpp
The file was modifiedllvm/lib/Transforms/IPO/Attributor.cpp
The file was modifiedllvm/lib/CodeGen/ModuloSchedule.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/CodeGen/MIRVRegNamerUtils.h
The file was modifiedllvm/lib/Target/ARM/MVEVPTBlockPass.cpp
Commit 1ff955305768b772be19ce8ee76246ab249bbe1c by david.green
[ARM] Fix for MVE load/store stack accesses
MVE loads and stores have a 7 bit immediate range, scaled by the length
of the type. This needs to be taught to the stack estimation code to
ensure that an emergency spill slot is reserved in case we run out of
registers when materialising stack indices.
Also the narrowing loads/stores can be created with frame indices even
though they do not accept SP as a register. We need in those cases to
make sure we have an emergency register to use as the frame base, as SP
can never be used.
Differential Revision: https://reviews.llvm.org/D67327
llvm-svn: 372114
The file was addedllvm/test/CodeGen/Thumb2/mve-stacksplot.mir
The file was modifiedllvm/lib/Target/ARM/ARMFrameLowering.cpp
Commit a2719f38c12d7208d2f931899e628d15562ee581 by llvm-dev
[LoopVectorize] Don't dereference a dyn_cast result. NFCI.
The static analyzer is warning about potential null dereferences of
dyn_cast<> results, we can use cast<> directly as we know that these
cases should all be CastInst, which is why its working atm and anyway
cast<> will assert if they aren't.
llvm-svn: 372116
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit c52a7093dfacacb65aabfff84c7e4fed854bb454 by llvm-dev
InterleavedAccessInfo - Don't dereference a dyn_cast result. NFCI.
llvm-svn: 372117
The file was modifiedllvm/lib/Analysis/VectorUtils.cpp
Commit f12a3da5a7aea556e326f50163c961c1ad5a4aa9 by llvm-dev
[X86] X86DAGToDAGISel::tryFoldLoad - assert root/parent pointers are
non-null. NFCI.
Silences a static analyzer warning.
llvm-svn: 372118
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Commit 47e95ff8133f2f24ea0aa5c4b0dc7e2b89cd11b7 by sven.vanhaastregt
[OpenCL] Tidy up some comments; NFC
llvm-svn: 372119
The file was modifiedclang/lib/Sema/OpenCLBuiltins.td
Commit 6cf896b284bbdd6330a73bf1c9e976db19678a41 by luismarques
[RISCV][NFC] Use NoRegister instead of 0 literal
Summary: Trivial cleanup.
Reviewers: asb, lenary
Reviewed By: lenary
Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal,
niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones,
rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei,
psnobl, benna, Jim, s.egerton, pzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67526
llvm-svn: 372120
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
Commit f1d069e54df350a807e9b90462485483139327ea by sam.parker
[ARM] Fix for buildbots
Add --verifymachineinstrs and update the remaining low overhead loop
tests.
llvm-svn: 372121
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir
Commit a3569aced05dd0238e286283da46bb55cd1f4c83 by grimar
[llvm-readobj/llvm-objdump] - Improve how tool locate the dynamic table
and report warnings about that.
Before this patch we gave a priority to a dynamic table found from the
section header.
It was discussed (here:
https://reviews.llvm.org/D67078?id=218356#inline-602082) that probably
preferring the table from PT_DYNAMIC is better, because it is what
runtime loader sees.
This patch makes the table from PT_DYNAMIC be chosen at first place if
it is available. But also it adds logic to fall back to SHT_DYNAMIC if
the table from the dynamic segment is broken or fall back to use no
table if both are broken.
It adds a few more diagnostic warnings for the logic above.
Differential revision: https://reviews.llvm.org/D67547
llvm-svn: 372122
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
The file was modifiedllvm/test/tools/llvm-readobj/elf-non-dynamic-in-pt-dynamic.test
The file was modifiedllvm/test/tools/llvm-readobj/elf-dynamic-not-in-pt-dynamic.test
The file was modifiedllvm/test/tools/llvm-readobj/elf-dynamic-malformed.test
Commit 84a2f5e8b7874e111c7212008ec2fb6372a4a2c7 by nicolasweber
gn build: (manually) merge r372076
llvm-svn: 372123
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/BUILD.gn
The file was addedllvm/utils/gn/secondary/llvm/unittests/Target/ARM/BUILD.gn
Commit 68b0977e646abda3254a1eed123f75183b4aad3d by erich.keane
Add SpellingNotCalculated to Attribute Enums to suppress UBSan warnings
UBSan downstreams noticed that the assignment of SpellingNotCalculated
to the spellings caused warnings.
llvm-svn: 372124
The file was modifiedclang/lib/CodeGen/CGDebugInfo.cpp
The file was modifiedclang/utils/TableGen/ClangAttrEmitter.cpp
The file was modifiedclang/lib/AST/MicrosoftMangle.cpp
The file was modifiedclang/lib/Sema/SemaType.cpp
Commit bdff164e0e07224948244ddc9bce5fd7052e09b9 by krasimir
Revert "[SLC] Preserve attrs for strncpy(x, "", y) -> memset(align 1 x,
'\0', y)"
Summary: This reverts commit r372101.
Causes ASAN build bot failures:
http://lab.llvm.org:8011/builders/sanitizer-ppc64be-linux/builds/14176
From
http://lab.llvm.org:8011/builders/sanitizer-ppc64be-linux/builds/14176/steps/64-bit%20check-asan/logs/stdio:
```
[ RUN      ] AddressSanitizer.StrNCatOOBTest
/home/buildbots/ppc64be-sanitizer/sanitizer-ppc64be/build/llvm-project/compiler-rt/lib/asan/tests/asan_str_test.cpp:462:
Failure Death test: strncat(to - 1, from, 0)
   Result: failed to die.
```
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67658
llvm-svn: 372125
The file was modifiedllvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
The file was modifiedllvm/test/Transforms/InstCombine/strncpy-1.ll
Commit 1d9ba08543dca55f1d5e8ba83d065fc2090ba106 by sam.parker
[ARM] Fix for buildbots
Remove setPreservesCFG from ARMConstantIslandPass and add a couple of
-verify-machine-dom-info instances into the existing codegen tests.
llvm-svn: 372126
The file was modifiedllvm/lib/Target/ARM/ARMConstantIslandPass.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/constant-islands.ll
The file was modifiedllvm/test/CodeGen/ARM/constant-islands-cfg.mir
Commit 167b3020753a339cc23fdd591b9d99543ab71038 by benny.kra
[RISCV] Unbreak the build
llvm-svn: 372127
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
Commit 957a6c6bedfa87e5384703724c18ddeada9e189e by benny.kra
[clangd] Fix another TSAN issue
llvm-svn: 372128
The file was modifiedclang-tools-extra/clangd/unittests/TUSchedulerTests.cpp
Commit 45b6ca5cd604d9dc0f957a5d80724acd54766f19 by yitzhakm
[clang-format] Fix cleanup of `AnnotatedLine` to include children nodes.
Summary: AnnotatedLine has a tree structure, and things like the body of
a lambda will be a child of the lambda expression. For example,
    [&]() { foo(a); };
will have an AnnotatedLine with a child:
    [&]() {};
    '- foo(a);
Currently, when the `Cleaner` class analyzes the affected lines, it does
not cleanup the lines' children nodes, which results in missed cleanup
opportunities, like the lambda body in the example above.
This revision extends the algorithm to visit children, thereby fixing
the above problem.
Patch by Eric Li.
Reviewers: krasimir
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D67659
llvm-svn: 372129
The file was modifiedclang/unittests/Format/CleanupTest.cpp
The file was modifiedclang/lib/Format/Format.cpp
Commit d0cc0a39be47cabd1325395197a3b7276f7b9fd9 by a.bataev
[OPENMP]Try to rework the test to pacify the buildbots, NFC.
llvm-svn: 372130
The file was modifiedclang/test/OpenMP/parallel_for_codegen.cpp
Commit 22a2209433a40508c2866ce8f547fcf319f83186 by david.green
[ARM] Reserve an emergency spill slot for fp16 addressing modes that
need it
Similar to D67327, but this time for the FP16 VLDR and VSTR instructions
that use the AddrMode5FP16 addressing mode. We need to reserve an
emergency spill slot for instructions that will be out of range to use
sp directly. AddrMode5FP16 is 8 bits with a scale of 2.
Differential Revision: https://reviews.llvm.org/D67483
llvm-svn: 372132
The file was modifiedllvm/lib/Target/ARM/ARMFrameLowering.cpp
The file was addedllvm/test/CodeGen/Thumb2/fp16-stacksplot.mir
Commit c42ca16cfa07da901b00940397e1a321623fd577 by david.green
[ARM] Fixup pipeline test. NFC
llvm-svn: 372133
The file was modifiedllvm/test/CodeGen/ARM/O3-pipeline.ll
Commit 91724b85307609f56eb2b547203107a578ea3fee by david.green
[ARM] Add a SelectTAddrModeImm7 for MVE narrow loads and stores
We were previously using the SelectT2AddrModeImm7 for both normal and
narrowing MVE loads/stores. As the narrowing instructions do not accept
sp as a register, it makes little sense to optimise a FrameIndex into
the load, only to have to recover that later on. This adds a
SelectTAddrModeImm7 which does not do that folding, and uses it for
narrowing load/store patterns.
Differential Revision: https://reviews.llvm.org/D67489
llvm-svn: 372134
The file was modifiedllvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-stack.ll
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
Commit b52650d57f86653de3ec259ee1ddaa19ec89d638 by clayborg
GSYM: add encoding and decoding to FunctionInfo
This patch adds encoding and decoding of the FunctionInfo objects along
with full error handling and tests. Full details of the FunctionInfo
encoding format appear in the FunctionInfo.h header file.
Differential Revision: https://reviews.llvm.org/D67506
llvm-svn: 372135
The file was modifiedllvm/unittests/DebugInfo/GSYM/GSYMTest.cpp
The file was modifiedllvm/include/llvm/DebugInfo/GSYM/FunctionInfo.h
The file was modifiedllvm/lib/DebugInfo/GSYM/FunctionInfo.cpp
Commit 39c5106eec79629f807589794d161bf2ba54fab0 by phosek
Move DK_Misexpect for compatability with
getNextAvailablePluginDiagnosticKind
First identified after D66324 landed.
Patch By: paulkirth Differential Revision:
https://reviews.llvm.org/D67648
llvm-svn: 372136
The file was modifiedllvm/include/llvm/IR/DiagnosticInfo.h
Commit 6b2d1346d8ed4c47fb61a249e0bb246dc9731144 by asbirlea
[MemorySSA] Update MSSA for non-conventional AA.
Summary: Regularly when moving an instruction that may not read or write
memory, the instruction is not modelled in MSSA, so not action is
necessary. For a non-conventional AA pipeline, MSSA needs to explicitly
check when creating accesses, so as to not model instructions that may
not read and write memory.
Reviewers: george.burgess.iv
Subscribers: Prazek, sanjoy.google, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67562
llvm-svn: 372137
The file was addedllvm/test/Analysis/MemorySSA/loop-rotate-disablebasicaa.ll
The file was modifiedllvm/lib/Analysis/MemorySSA.cpp
Commit 4e9082ef95db5d760df4cce00a4351fa122176d6 by asbirlea
[MemorySSA] Fix phi insertion when inserting a def.
Summary: When inserting a Def, the current algorithm is walking edges
backward and inserting new Phis where needed. There may be additional
Phis needed in the IDF of the newly inserted Def and Phis. Adding Phis
in the IDF of the Def was added ina  previous patch, but we may also
need other Phis in the IDF of the newly added Phis.
Reviewers: george.burgess.iv
Subscribers: Prazek, sanjoy.google, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67637
llvm-svn: 372138
The file was modifiedllvm/lib/Analysis/MemorySSAUpdater.cpp
The file was addedllvm/test/Analysis/MemorySSA/pr43320.ll
Commit 1461fb6e783cb946b061f66689b419f74f7fad63 by nemanja.i.ibm
[PowerPC] Exploit single instruction load-and-splat for word and
doubleword
We currently produce a load, followed by (possibly a move for integers
and) a splat as separate instructions. VSX has always had a splatting
load for doublewords, but as of Power9, we have it for words as well.
This patch just exploits these instructions.
Differential revision: https://reviews.llvm.org/D63624
llvm-svn: 372139
The file was modifiedllvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll
The file was modifiedllvm/test/CodeGen/PowerPC/build-vector-tests.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was addedllvm/test/CodeGen/PowerPC/load-and-splat.ll
The file was modifiedllvm/test/CodeGen/PowerPC/power9-moves-and-splats.ll
The file was modifiedllvm/test/CodeGen/PowerPC/qpx-load-splat.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.h
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrAltivec.td
The file was modifiedllvm/test/CodeGen/PowerPC/swaps-le-7.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrVSX.td
Commit 5abd6f46ae8ae1a8b0f52b60fb52e1ba444b3d9b by david.bolvansky
[ASAN] Adjust asan tests due to new optimizations
llvm-svn: 372141
The file was modifiedcompiler-rt/lib/asan/tests/asan_str_test.cpp
Commit 0c0de794f1affc7460eb90626b8483e4a0cbde6c by david.bolvansky
Reland "[SLC] Preserve attrs for strncpy(x, "", y) -> memset(align 1 x,
'\0', y)"
llvm-svn: 372142
The file was modifiedllvm/test/Transforms/InstCombine/strncpy-1.ll
The file was modifiedllvm/lib/Transforms/Utils/SimplifyLibCalls.cpp