FailedChanges

Summary

  1. llvm-reduce: Add pass to reduce instructions (details)
  2. gn build: Merge r372282 (details)
  3. [WebAssembly] Sort output data sections to place .bss last (details)
  4. GlobalISel: Don't materialize immarg arguments to intrinsics (details)
  5. AMDGPU/GlobalISel: Fix RegBankSelect G_SMULH/G_UMULH pre-gfx9 (details)
  6. MachineScheduler: Fix assert from not checking subregs (details)
  7. Fix typo (details)
  8. AMDGPU/GlobalISel: Attempt to RegBankSelect image intrinsics (details)
  9. AMDGPU/GlobalISel: RegBankSelect llvm.amdgcn.raw.buffer.{load|store} (details)
  10. AMDGPU/GlobalISel: RegBankSelect struct buffer load/store (details)
  11. AMDGPU/GlobalISel: Select llvm.amdgcn.raw.buffer.store (details)
  12. AMDGPU/GlobalISel: Select llvm.amdgcn.raw.buffer.store.format (details)
  13. [CLANG][BPF] change __builtin_preserve_access_index() signature (details)
Commit 798fe477e39db137ec0f76c94cbee17761bdef0a by dblaikie
llvm-reduce: Add pass to reduce instructions
Patch by Diego TreviƱo!
Differential Revision: https://reviews.llvm.org/D66263
llvm-svn: 372282
The file was addedllvm/test/Reduce/Inputs/remove-instructions.py
The file was modifiedllvm/test/Reduce/Inputs/remove-bbs.py
The file was modifiedllvm/tools/llvm-reduce/CMakeLists.txt
The file was modifiedllvm/test/Reduce/remove-global-vars.ll
The file was addedllvm/tools/llvm-reduce/deltas/ReduceInstructions.h
The file was addedllvm/tools/llvm-reduce/deltas/ReduceInstructions.cpp
The file was addedllvm/test/Reduce/remove-instructions.ll
The file was modifiedllvm/test/Reduce/Inputs/remove-global-vars.py
The file was modifiedllvm/tools/llvm-reduce/DeltaManager.h
Commit 98a57332ef0e4b859e74a3a43f7f31e9ff1683e0 by llvmgnsyncbot
gn build: Merge r372282
llvm-svn: 372283
The file was modifiedllvm/utils/gn/secondary/llvm/tools/llvm-reduce/BUILD.gn
Commit 21143b93a6ee1121b96ee7f4a75ee542580ba57c by tlively
[WebAssembly] Sort output data sections to place .bss last
Summary: This was always the intended behavior, but had not been
implemented. This ordering is important for Emscripten when generating
.mem files while compiling to JS, since only zeros at the end of
initialized memory can be dropped.
Fixes https://github.com/emscripten-core/emscripten/issues/8999
Reviewers: sbc100
Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67736
llvm-svn: 372284
The file was modifiedlld/test/wasm/data-segment-merging.ll
The file was modifiedlld/test/wasm/data-layout.ll
The file was modifiedlld/test/wasm/tls-align.ll
The file was modifiedlld/wasm/OutputSegment.h
The file was modifiedlld/test/wasm/reloc-addend.ll
The file was modifiedlld/test/wasm/tls.ll
The file was addedlld/test/wasm/custom-section-name.ll
The file was modifiedlld/wasm/Writer.cpp
The file was modifiedlld/test/wasm/data-segments.ll
The file was modifiedlld/test/wasm/relocatable.ll
Commit d8399d12cd851dacd8f3e1be8b7ca79372626f38 by Matthew.Arsenault
GlobalISel: Don't materialize immarg arguments to intrinsics
Encode them directly as an imm argument to G_INTRINSIC*.
Since now intrinsics can now define what parameters are required to be
immediates, avoid using registers for them. Intrinsics could potentially
want a constant that isn't a legal register type. Also, since G_CONSTANT
is subject to CSE and legalization, transforms could potentially obscure
the value (and create extra work for the selector). The register bank of
a G_CONSTANT is also meaningful, so this could throw off future folding
and legalization logic for AMDGPU.
This will be much more convenient to work with than needing to call
getConstantVRegVal and checking if it may have failed for every constant
intrinsic parameter. AMDGPU has quite a lot of intrinsics wth immarg
operands, many of which need inspection during lowering. Having to find
the value in a register is going to add a lot of boilerplate and waste
compile time.
SelectionDAG has always provided TargetConstant for constants which
should not be legalized or materialized in a register. The distinction
between Constant and TargetConstant was somewhat fuzzy, and there was no
automatic way to force usage of TargetConstant for certain intrinsic
parameters. They were both ultimately ConstantSDNode, and it was
inconsistently used. It was quite easy to mis-select an instruction
requiring an immediate. For SelectionDAG, start emitting TargetConstant
for these arguments, and using timm to match them.
Most of the work here is to cleanup target handling of constants. Some
targets process intrinsics through intermediate custom nodes, which need
to preserve TargetConstant usage to match the intrinsic expectation.
Pattern inputs now need to distinguish whether a constant is merely
compatible with an operand or whether it is mandatory.
The GlobalISelEmitter needs to treat timm as a special case of a leaf
node, simlar to MachineBasicBlock operands. This should also enable
handling of patterns for some G_* instructions with immediates, like
G_FENCE or G_EXTRACT.
This does include a workaround for a crash in GlobalISelEmitter when ARM
tries to uses "imm" in an output with a "timm" pattern source.
llvm-svn: 372285
The file was modifiedllvm/lib/Target/AMDGPU/BUFInstructions.td
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll
The file was modifiedllvm/lib/Target/ARM/ARMInstrInfo.td
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/lib/Target/ARM/ARMInstrThumb2.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZOperators.td
The file was modifiedllvm/lib/Target/Mips/MipsDSPInstrInfo.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.sleep.ll
The file was modifiedllvm/lib/Target/X86/X86InstrSSE.td
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll
The file was modifiedllvm/lib/Target/X86/X86InstrMMX.td
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir
The file was modifiedllvm/lib/Target/Mips/MipsInstrInfo.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
The file was modifiedllvm/lib/Target/X86/X86InstrSystem.td
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll
The file was modifiedllvm/include/llvm/Target/TargetSelectionDAG.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
The file was modifiedllvm/lib/Target/AMDGPU/SOPInstructions.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZOperands.td
The file was modifiedllvm/lib/Target/Mips/Mips64InstrInfo.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZPatterns.td
The file was modifiedllvm/lib/Target/AMDGPU/VOP1Instructions.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrVSX.td
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepOperands.td
The file was modifiedllvm/lib/Target/Mips/MipsSEISelLowering.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrAltivec.td
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td
The file was modifiedllvm/lib/Target/AMDGPU/DSInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrBulkMemory.td
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was addedllvm/test/TableGen/immarg.td
The file was modifiedllvm/lib/Target/X86/X86InstrTSX.td
The file was modifiedllvm/lib/Target/X86/X86InstrAVX512.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonIntrinsics.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoA.td
The file was modifiedllvm/lib/Target/Mips/MipsMSAInstrInfo.td
The file was modifiedllvm/lib/Target/X86/X86InstrXOP.td
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrVector.td
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
Commit 22e2c09515e33f11955e7af6dfd09de093c5385b by Matthew.Arsenault
AMDGPU/GlobalISel: Fix RegBankSelect G_SMULH/G_UMULH pre-gfx9
The scalar versions were only introduced in gfx9.
llvm-svn: 372286
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
Commit c189f023ac44d64e7d245e08dee53003da74f5d1 by Matthew.Arsenault
MachineScheduler: Fix assert from not checking subregs
The assert would fail if there was a dead def of a subregister if there
was a previous use of a different subregister.
llvm-svn: 372287
The file was modifiedllvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
The file was modifiedllvm/lib/CodeGen/ScheduleDAGInstrs.cpp
The file was addedllvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
Commit 01213407c4114f5b587b29eae11f0a417666f965 by Matthew.Arsenault
Fix typo
llvm-svn: 372288
The file was modifiedllvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
Commit a30d022db6d4c0b7f16c50c322667eedd45553d2 by Matthew.Arsenault
AMDGPU/GlobalISel: Attempt to RegBankSelect image intrinsics
Images should always have 2 consecutive, mandatory SGPR arguments.
llvm-svn: 372289
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
Commit a62ef58346818bbd30201dc81a4d10ecfc1c9ca9 by Matthew.Arsenault
AMDGPU/GlobalISel: RegBankSelect llvm.amdgcn.raw.buffer.{load|store}
llvm-svn: 372290
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.store.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit 838ff36553ae4933134ee0a383a238bbedcba0ec by Matthew.Arsenault
AMDGPU/GlobalISel: RegBankSelect struct buffer load/store
llvm-svn: 372291
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
Commit 67f1f6ff8c07b5eef7239679a6b534efe933ceaa by Matthew.Arsenault
AMDGPU/GlobalISel: Select llvm.amdgcn.raw.buffer.store
llvm-svn: 372292
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was removedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.store.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
Commit 494243597b46350a248ee25efb0e3a728fc5900c by Matthew.Arsenault
AMDGPU/GlobalISel: Select llvm.amdgcn.raw.buffer.store.format
This needs special handling due to some subtargets that have a
nonstandard register layout for f16 vectors
Also reject some illegal types on other targets.
llvm-svn: 372293
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
Commit c15aa241f8213334f6980b7981cee1f28f81112a by yhs
[CLANG][BPF] change __builtin_preserve_access_index() signature
The clang intrinsic __builtin_preserve_access_index() currently has
signature:
const void * __builtin_preserve_access_index(const void * ptr)
This may cause compiler warning when:
- parameter type is "volatile void *" or "const volatile void *", or
- the assign-to type of the intrinsic does not have "const" qualifier.
Further, this signature does not allow dereference of the builtin result
pointer as it is a "const void *" type, which adds extra step for the
user to do type casting.
Let us change the signature to:
PointerT __builtin_preserve_access_index(PointerT ptr) such that the
result and argument types are the same. With this, directly
dereferencing the builtin return value becomes possible.
Differential Revision: https://reviews.llvm.org/D67734
llvm-svn: 372294
The file was modifiedclang/test/Sema/builtin-preserve-access-index.c
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/docs/LanguageExtensions.rst
The file was modifiedclang/include/clang/Basic/Builtins.def
The file was modifiedclang/lib/Sema/SemaChecking.cpp