Commit
a7cac2bd4b6812ea6b59b5fa0298eadf3815a3b0
by aminim[MLIR] Fix broken link locations after move to monorepo I used the codemod python tool to do this with the following commands: codemod 'tensorflow/mlir/blob/master/include' 'llvm/llvm-project/blob/master/mlir/include' codemod 'tensorflow/mlir/blob/master' 'llvm/llvm-project/blob/master/mlir' codemod 'tensorflow/mlir' 'llvm-project/llvm' Differential Revision: https://reviews.llvm.org/D72244
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 | mlir/docs/Tutorials/Toy/Ch-7.md |
 | mlir/docs/Dialects/Vector.md |
 | mlir/examples/toy/Ch6/include/toy/Dialect.h |
 | mlir/examples/toy/Ch4/include/toy/Dialect.h |
 | mlir/examples/toy/Ch7/include/toy/Dialect.h |
 | mlir/examples/toy/README.md |
 | mlir/examples/toy/Ch3/include/toy/Dialect.h |
 | mlir/examples/toy/Ch5/include/toy/Dialect.h |
 | mlir/examples/toy/Ch2/include/toy/Dialect.h |
Commit
671544c25b1215433bc22d475db7eaef51096ea5
by czhengsz[PowerPC] [NFC] set instruction number as 1st priority of lsr cost model.
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 | llvm/test/CodeGen/PowerPC/lsr-insns-cost.ll |
Commit
0136f226c4e46258ea73fcb994f6559cec4a9aa2
by maskray[MC] Don't resolve relocations referencing STB_LOCAL STT_GNU_IFUNC
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 | llvm/lib/MC/ELFObjectWriter.cpp |
 | llvm/test/MC/ELF/target-in-same-section.s |
Commit
7cd429f27d4886bb841ed0e3702e970f5f6cccd1
by maskray[ELF] Add -z force-ibt and -z shstk for Intel Control-flow Enforcement Technology This patch is a joint work by Rui Ueyama and me based on D58102 by Xiang Zhang. It adds Intel CET (Control-flow Enforcement Technology) support to lld. The implementation follows the draft version of psABI which you can download from https://github.com/hjl-tools/x86-psABI/wiki/X86-psABI. CET introduces a new restriction on indirect jump instructions so that you can limit the places to which you can jump to using indirect jumps. In order to use the feature, you need to compile source files with -fcf-protection=full. * IBT is enabled if all input files are compiled with the flag. To force enabling ibt, pass -z force-ibt. * SHSTK is enabled if all input files are compiled with the flag, or if -z shstk is specified. IBT-enabled executables/shared objects have two PLT sections, ".plt" and ".plt.sec". For the details as to why we have two sections, please read the comments. Reviewed By: xiangzhangllvm Differential Revision: https://reviews.llvm.org/D59780
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 | lld/ELF/Options.td |
 | lld/docs/ld.lld.1 |
 | lld/ELF/Config.h |
 | lld/ELF/SyntheticSections.h |
 | lld/ELF/SyntheticSections.cpp |
 | lld/test/ELF/x86-64-feature-cet.s |
 | lld/test/ELF/x86-64-cet.s |
 | lld/ELF/Writer.cpp |
 | lld/ELF/Arch/X86.cpp |
 | lld/test/ELF/i386-feature-cet.s |
 | lld/ELF/Arch/X86_64.cpp |
 | lld/test/ELF/i386-cet.s |
 | lld/ELF/Driver.cpp |
 | lld/ELF/Target.h |
Commit
84637408f2e63821014974dac08dee50bb197c1b
by protze[OpenMP][Tool] Make tests for archer dependent on TSan If the openmp project is built standalone, the test compiler is feature tested for an available -fsanitize=thread flag. If the openmp project is built as part of llvm, the target tsan is needed to test archer. An additional line (requires tsan) was introduced to the tests, this patch updates the line numbers for the race. Follow-up for 77ad98c Reviewed By: jdoerfert Differential Revision: https://reviews.llvm.org/D71914
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 | openmp/tools/archer/tests/races/lock-unrelated.c |
 | openmp/tools/archer/tests/races/task-taskwait-nested.c |
 | openmp/tools/archer/tests/races/task-dependency.c |
 | openmp/tools/archer/tests/races/task-taskgroup-unrelated.c |
 | openmp/tools/archer/tests/lit.cfg |
 | openmp/tools/archer/tests/races/task-two.c |
 | openmp/tools/archer/tests/lit.site.cfg.in |
 | openmp/tools/archer/tests/CMakeLists.txt |
 | openmp/tools/archer/tests/races/critical-unrelated.c |
 | openmp/tools/archer/tests/races/lock-nested-unrelated.c |
 | openmp/tools/archer/tests/races/parallel-simple.c |
 | openmp/cmake/DetectTestCompiler/CMakeLists.txt |
 | openmp/cmake/OpenMPTesting.cmake |
Commit
d9819f366233e53427d0929729a58f85dc748cfb
by maskray[ELF] Delete unintended --force-bti
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 | lld/ELF/Options.td |
Commit
ed810da73270267082c347bc2919eebb7978a2fe
by protze[OpenMP][Tool] Improving stack trace for Archer The OpenMP runtime is not instrumented, so entering the runtime leaves no hint on the source line of the pragma on ThreadSanitizer's function stack. This patch adds function entry/exit annotations for OpenMP parallel regions, and synchronization regions (barrier, taskwait, taskgroup). Reviewed By: jdoerfert Differential Revision: https://reviews.llvm.org/D70408
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 | openmp/tools/archer/ompt-tsan.cpp |
Commit
63c3691f79179db9a16f260f1cf81475fdfef060
by jay.foad[AMDGPU] Add gfx9 assembler and disassembler test cases Summary: This adds assembler tests for cases that were previously only in the disassembler tests, and vice versa. Reviewers: rampitec, arsenm, nhaehnle Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72592
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 | llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt |
 | llvm/test/MC/AMDGPU/gfx9_asm_all.s |
Commit
0950de264e37264b9f767a898bd839d9fcb7328f
by jay.foad[AMDGPU] Improve error checking in gfx10 assembler tests Summary: This adds checks that the expected error was actually reported against the correct instruction, and fixes a couple of problems that that showed up: one incorrect W32-ERR: v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD // W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x00,0x06,0x06] -// W32-ERR: error: invalid operand for instruction +// W32-ERR: error: {{instruction not supported on this GPU|invalid operand for instruction}} and one missing W32-ERR: v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD // W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x06,0x06] +// W32-ERR: error: invalid operand for instruction Reviewers: rampitec, arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72611
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 | llvm/test/MC/AMDGPU/gfx10_asm_all.s |
Commit
440ce5164f52a6b7cdf70322cc1c95656cac9aa9
by jay.foad[AMDGPU] Remove duplicate gfx10 assembler and disassembler tests Summary: Depends on D72611. Reviewers: rampitec, arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72616
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 | llvm/test/MC/AMDGPU/gfx10_asm_all.s |
 | llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt |
Commit
61b6a4e82653e1209126404d33ad20a268f55db1
by Raphael Isemann[lldb] Fix that SBThread.GetStopDescription is returning strings with uninitialized memory at the end. Summary: `SBThread.GetStopDescription` is a curious API as it takes a buffer length as a parameter that specifies how many bytes the buffer we pass has. Then we fill the buffer until the specified length (or the length of the stop description string) and return the string length. If the buffer is a nullptr however, we instead return how many bytes we would have written to the buffer so that the user can allocate a buffer with the right size and pass that size to a subsequent `SBThread.GetStopDescription` call. Funnily enough, it is not possible to pass a nullptr via the Python SWIG bindings, so that might be the first API in LLDB that is not only hard to use correctly but impossible to use correctly. The only way to call this function via Python is to throw in a large size limit that is hopefully large enough to contain the stop description (otherwise we only get the truncated stop description). Currently passing a size limit that is smaller than the returned stop description doesn't cause the Python bindings to return the stop description but instead the truncated stop description + uninitialized characters at the end of the string. The reason for this is that we return the result of `snprintf` from the method which returns the amount of bytes that *would* have been written (which is larger than the buffer). This causes our Python bindings to return a string that is as large as full stop description but the buffer that has been filled is only as large as the passed in buffer size. This patch fixes this issue by just recalculating the string length in our buffer instead of relying on the wrong return value. We also have to do this in a new type map as the old type map is also used for all methods with the given argument pair `char *dst, size_t dst_len` (e.g. SBProcess.GetSTDOUT`). These methods have different semantics for these arguments and don't null-terminate the returned buffer (they instead return the size in bytes) so we can't change the existing typemap without breaking them. Reviewers: labath, jingham Reviewed By: labath Subscribers: clayborg, shafik, abidh, JDevlieghere, lldb-commits Tags: #lldb Differential Revision: https://reviews.llvm.org/D72086
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 | lldb/bindings/python/python-typemaps.swig |
 | lldb/packages/Python/lldbsuite/test/python_api/thread/TestThreadAPI.py |
 | lldb/bindings/interface/SBThread.i |
Commit
f18370fe0e7576fb9947e49d66f7a6962c6822ce
by Raphael Isemann[lldb] Don't defend against internal LLVM errors in IRInterpreter Summary: Whenever we cast an LLVM instruction to one of its subclasses, we do a double check if the RTTI enum value actually allows us to cast the class. I don't see a way this can ever happen as even when LLVM's RTTI system has some corrupt internal state (which we probably should not test in the first place) we just reuse LLVM RTTI to do the second check. This also means that if we ever make an actual programming error in this function (e.g., have a enum value and then cast it to a different subclass), we just silently fall back to the JIT in our tests. We also can't test this code in any reasonable way. This removes the checks and uses `llvm::cast` instead which will raise a fatal error when casting fails. Reviewers: labath, mib Reviewed By: labath Subscribers: abidh, JDevlieghere, lldb-commits Tags: #lldb Differential Revision: https://reviews.llvm.org/D72596
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 | lldb/source/Expression/IRInterpreter.cpp |
Commit
547abdd921e45fd65a2fa60f21715facb4af31b2
by sam.mccall[mlir] Fix -Wunused
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 | mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp |
Commit
eca44745871bc46728903aaa262abc6344d4f959
by Stanislav.Mekhanoshin[AMDGPU] Fix getInstrLatency() always returning 1 We do not have InstrItinerary so generic getInstLatency() was always defaulting to return 1 cycle. We need to use TargetSchedModel instead to compute an instruction's latency. Differential Revision: https://reviews.llvm.org/D72655
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 | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp |
 | llvm/lib/Target/AMDGPU/SIInstrInfo.h |
 | llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir |
 | llvm/test/CodeGen/AMDGPU/max.i16.ll |
Commit
d8ffd601d523fa0c0a55e25e62af9ffaa618629d
by Raphael Isemann[lldb][NFC] Rewrite python_api/rdar-12481949 test Summary: This renames the test `rdar-12481949` to `get-value-32bit-int` as it just tests that we return the correct result get calling GetValueAsSigned/GetValueAsUnsigned on 32-bit integers. It also deletes all the strange things going on in this test including resetting the data formatters (which are to my knowledge not used to calculate scalar values) and testing Python's long integers (let's just assume that our Python distribution works correctly). Also modernises the setup code. Reviewers: labath, aprantl Reviewed By: aprantl Subscribers: JDevlieghere, lldb-commits Tags: #lldb Differential Revision: https://reviews.llvm.org/D72593
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 | lldb/packages/Python/lldbsuite/test/python_api/rdar-12481949/main.cpp |
 | lldb/packages/Python/lldbsuite/test/python_api/rdar-12481949/Makefile |
 | lldb/packages/Python/lldbsuite/test/python_api/get-value-32bit-int/Makefile |
 | lldb/packages/Python/lldbsuite/test/python_api/get-value-32bit-int/main.cpp |
 | lldb/packages/Python/lldbsuite/test/python_api/get-value-32bit-int/TestGetValue32BitInt.py |
 | lldb/packages/Python/lldbsuite/test/python_api/rdar-12481949/Test-rdar-12481949.py |
Commit
6d8abe424a77f736fbed114eeac574b9bfe6b0c1
by bion[libcxx] [test] Add casts to avoid signed/unsigned mismatch warnings on MSVC++ A bug was filed that these warnings should not be emitted as DevCom-883961. ( https://developercommunity.visualstudio.com/content/problem/883961/c4389-signedunsigned-mismatch-should-not-be-emitte.html )
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 | libcxx/test/std/algorithms/alg.modifying.operations/alg.reverse/reverse_copy.pass.cpp |
 | libcxx/test/std/algorithms/alg.modifying.operations/alg.remove/remove_copy.pass.cpp |
 | libcxx/test/std/algorithms/alg.modifying.operations/alg.remove/remove_copy_if.pass.cpp |
Commit
ad741853c38880dff99cd5b5035b8965c5a73011
by Stanislav.Mekhanoshin[AMDGPU] Model distance to instruction in bundle This change allows to model the height of the instruction within a bundle for latency adjustment purposes. Differential Revision: https://reviews.llvm.org/D72669
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 | llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp |
 | llvm/test/CodeGen/AMDGPU/bundle-latency.mir |
Commit
ec6579fc047f9ac18588b833dfde0b69064e013a
by grimar[llvm-readobj][test] - Fix grammar in comments. This addresses post commit review comments for D71766.
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 | llvm/test/tools/llvm-readobj/ELF/file-header-abi-version.test |
 | llvm/test/tools/llvm-readobj/ELF/file-header-os-abi.test |
Commit
45924eb4671692b3fa9fd52fe39c81ec0647a848
by malcolm.parsons[clang-tidy] Ignore implicit casts in modernize-use-default-member-init Summary: Initialising a pointer from nullptr involves an implicit cast. Ignore it after getting initialiser from InitListExpr. Fixes: PR44440 Reviewers: aaron.ballman, alexfh, JonasToth Reviewed By: JonasToth Subscribers: xazax.hun, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D72630
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 | clang-tools-extra/clang-tidy/modernize/UseDefaultMemberInitCheck.cpp |
 | clang-tools-extra/test/clang-tidy/checkers/modernize-use-default-member-init.cpp |
Commit
3388b0f59dcc7813278c753f96b66229f290cc59
by simon.tatham[TableGen] Introduce a `defvar` statement. Summary: This allows you to define a global or local variable to an arbitrary value, and refer to it in subsequent definitions. The main use I anticipate for this is if you have to compute some difficult function of the parameters of a multiclass, and then use it many times. For example: multiclass Foo<int i, string s> { defvar op = !cast<BaseClass>("whatnot_" # s # "_" # i); def myRecord { dag a = (op this, (op that, the other), (op x, y, z)); int b = op.subfield; } def myOtherRecord<"template params including", op>; } There are a couple of ways to do this already, but they're not really satisfactory. You can replace `defvar x = y` with a loop over a singleton list, `foreach x = [y] in { ... }` - but that's unintuitive to someone who hasn't seen that workaround idiom before, and requires an extra pair of braces that you often didn't really want. Or you can define a nested pair of multiclasses, with the inner one taking `x` as a template parameter, and the outer one instantiating it just once with the desired value of `x` computed from its other parameters - but that makes it awkward to sequentially compute each value based on the previous ones. I think `defvar` makes things considerably easier. You can also use `defvar` at the top level, where it inserts globals into the same map used by `defset`. That allows you to define global constants without having to make a dummy record for them to live in: defvar MAX_BUFSIZE = 512; // previously: // def Dummy { int MAX_BUFSIZE = 512; } // and then refer to Dummy.MAX_BUFSIZE everywhere Reviewers: nhaehnle, hfinkel Reviewed By: hfinkel Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71407
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 | llvm/docs/TableGen/LangRef.rst |
 | llvm/lib/TableGen/TGLexer.cpp |
 | llvm/lib/TableGen/TGLexer.h |
 | llvm/lib/TableGen/TGParser.h |
 | llvm/test/TableGen/defvar.td |
 | llvm/lib/TableGen/TGParser.cpp |
Commit
ddbc0b1e516407a24d986a1998026f1ac5864270
by simon.tatham[TableGen] Introduce an if/then/else statement. Summary: This allows you to make some of the defs in a multiclass or `foreach` conditional on an expression computed from the parameters or iteration variables. It was already possible to simulate an if statement using a `foreach` with a dummy iteration variable and a list constructed using `!if` so that it had length 0 or 1 depending on the condition, e.g. foreach unusedIterationVar = !if(condition, [1], []<int>) in { ... } But this syntax is nicer to read, and also more convenient because it allows an else clause. To avoid upheaval in the implementation, I've implemented `if` as pure syntactic sugar on the `foreach` implementation: internally, `ParseIf` actually does construct exactly the kind of foreach shown above (and another reversed one for the else clause if present). Reviewers: nhaehnle, hfinkel Reviewed By: hfinkel Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71474
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 | llvm/docs/TableGen/LangRef.rst |
 | llvm/lib/TableGen/TGLexer.cpp |
 | llvm/lib/TableGen/TGParser.cpp |
 | llvm/test/TableGen/ifstmt.td |
 | llvm/test/TableGen/defvar.td |
 | llvm/lib/TableGen/TGParser.h |
 | llvm/lib/TableGen/TGLexer.h |
Commit
41b520188820a732e6de4865c08704f412013209
by sam.mccall[Target] Fix uninitialized value in 10c11e4e2d05cf0e8f8251f50d84ce77eb1e9b8d
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 | llvm/include/llvm/Target/TargetOptions.h |
Commit
72ca86fd34ecc5f7ccbaf923d2d508dad2a6a64c
by anna.welker[ARM][MVE] Masked gathers from base + vector of offsets Enables the masked gather pass to create a masked gather loading from a base and vector of offsets. This also enables v8i16 and v16i8 gather loads. Differential Revision: https://reviews.llvm.org/D72330
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 | llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll |
 | llvm/test/CodeGen/Thumb2/mve-gather-scatter-opt.ll |
 | llvm/test/CodeGen/Thumb2/mve-gather-ind8-unscaled.ll |
 | llvm/test/CodeGen/Thumb2/mve-gather-ind32-unscaled.ll |
 | llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp |
 | llvm/test/CodeGen/Thumb2/mve-gather-ind16-scaled.ll |
 | llvm/test/CodeGen/Thumb2/mve-gather-ind32-scaled.ll |
 | llvm/test/CodeGen/Thumb2/mve-gather-ind16-unscaled.ll |
Commit
018b042593f007456b0695421942ec84ec816a30
by Adrian Prantl[mlir] Add loop.parallel, loop.reduce and loop.reduce.return operations. Summary: These operations can be used to specify a loop nest with a body that can contain reductions. The iteration space can be iterated in any order. RFC: https://groups.google.com/a/tensorflow.org/d/topic/mlir/pwtSgiKFPis/discussion Differential Revision: https://reviews.llvm.org/D72394
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 | mlir/lib/Dialect/LoopOps/LoopOps.cpp |
 | mlir/include/mlir/Dialect/LoopOps/LoopOps.td |
 | mlir/test/Dialect/Loops/ops.mlir |
 | mlir/test/Dialect/Loops/invalid.mlir |
Commit
5a6eae3dea2342c2a83e4502de43927808f8ca21
by Adrian Prantl[mlir] Ran git-clang-format. Summary: I forgot to ran git-clang-format before committing.
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 | mlir/lib/Dialect/LoopOps/LoopOps.cpp |
Commit
9492e9d8cfd356109276da5aa926b297db0e16db
by Raphael Isemann[lldb][NFC] Cleanup ClangASTContext::CompleteTagDeclarationDefinition Makes this function exit early instead of nesting if statements. Also removed all the if (tag_type->getDecl()) checks. If we created a TagType with a nullptr as a Decl then Clang would have already deferenced that nullptr during TagType creation so there is no point in gracefully handling a nullptr here.
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 | lldb/source/Symbol/ClangASTContext.cpp |
Commit
4624a1e8ac8a3f69cc887403b976f538f587744a
by herhut[mlir] Create a gpu.module operation for the GPU Dialect. Summary: This is based on the use of code constantly checking for an attribute on a model and instead represents the distinct operaion with a different op. Instead, this op can be used to provide better filtering. Reviewers: herhut, mravishankar, antiagainst, rriddle Reviewed By: herhut, antiagainst, rriddle Subscribers: liufengdb, aartbik, jholewinski, mgorny, mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache, csigg, arpith-jacob, mgester, lucyrfox, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72336
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 | mlir/lib/Conversion/GPUToCUDA/ConvertKernelFuncToCubin.cpp |
 | mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp |
 | mlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp |
 | mlir/test/Dialect/GPU/outlining.mlir |
 | mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir |
 | mlir/tools/mlir-cuda-runner/mlir-cuda-runner.cpp |
 | mlir/test/Conversion/GPUToCUDA/lower-nvvm-kernel-to-cubin.mlir |
 | mlir/include/mlir/Conversion/GPUToNVVM/GPUToNVVMPass.h |
 | mlir/lib/Conversion/GPUToCUDA/ConvertLaunchFuncToCudaCalls.cpp |
 | mlir/test/Dialect/GPU/invalid.mlir |
 | mlir/include/mlir/Conversion/GPUToCUDA/GPUToCUDAPass.h |
 | mlir/test/Conversion/GPUToCUDA/lower-launch-func-to-cuda.mlir |
 | mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRV.td |
 | mlir/test/Conversion/GPUToSPIRV/load-store.mlir |
 | mlir/include/mlir/Dialect/GPU/GPUOps.td |
 | mlir/test/Conversion/GPUToSPIRV/loop.mlir |
 | mlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRVPass.cpp |
 | mlir/test/Conversion/GPUToSPIRV/builtins.mlir |
 | mlir/test/Dialect/GPU/ops.mlir |
 | mlir/test/Conversion/GPUToNVVM/memory-attrbution.mlir |
 | mlir/test/Conversion/GPUToSPIRV/simple.mlir |
 | mlir/lib/Conversion/GPUToSPIRV/CMakeLists.txt |
 | mlir/lib/Dialect/GPU/Transforms/KernelOutlining.cpp |
 | mlir/lib/Dialect/GPU/IR/GPUDialect.cpp |
Commit
3d6c492d7a9830a1a39b85dfa215743581d52715
by jrtc27[RISCV] Fix ILP32D lowering for double+double/double+int return types Summary: Previously, since these aggregates are > 2*XLen, Clang would think they were being returned indirectly and thus would decrease the number of available GPRs available by 1. For long argument lists this could lead to a struct argument incorrectly being passed indirectly. Reviewers: asb, lenary Reviewed By: asb, lenary Subscribers: luismarques, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, lenary, s.egerton, pzheng, sameer.abuasal, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D69590
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 | clang/test/CodeGen/riscv32-ilp32d-abi.c |
 | clang/lib/CodeGen/TargetInfo.cpp |
Commit
d6ea8ff0d74bfe5cd181ccfe91c2c300c5f7a35d
by zinenko[mlir] Fix translation of splat constants to LLVM IR Summary: When converting splat constants for nested sequential LLVM IR types wrapped in MLIR, the constant conversion was erroneously assuming it was always possible to recursively construct a constant of a sequential type given only one value. Instead, wait until all sequential types are unpacked recursively before constructing a scalar constant and wrapping it into the surrounding sequential type. Subscribers: mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, aartbik, liufengdb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72688
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 | mlir/test/Target/llvmir.mlir |
 | mlir/lib/Target/LLVMIR/ModuleTranslation.cpp |
Commit
e73b20c57dc7a8c847ebadeb7e19c08ec84f5bd7
by sam.parker[ARM][MVE] Disallow VPSEL for tail predication Due to the current way that we collect predicated instructions, we can't easily handle vpsel in tail predicated loops. There are a couple of issues: 1) It will use the VPR as a predicate operand, but doesn't have to be instead a VPT block, which means we can assert while building up the VPT block because we don't find another VPST to being a new one. 2) VPSEL still requires a VPR operand even after tail predicating, which means we can't remove it unless there is another instruction, such as vcmp, that can provide the VPR def. The first issue should be a relatively simple fix in the logic of the LowOverheadLoops pass, whereas the second will require us to represent the 'implicit' tail predication with an explicit value. Differential Revision: https://reviews.llvm.org/D72629
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 | llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp |
 | llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir |
 | llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir |
 | llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir |
 | llvm/lib/Target/ARM/ARMInstrMVE.td |
 | llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir |
 | llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir |
Commit
a43b0065c5c78eba3fb83881fb628f5b8182db64
by llvm-dev[SelectionDAG] ComputeKnownBits - merge getValidMinimumShiftAmountConstant() and generic ISD::SRL handling. As mentioned by @nikic on rGef5debac4302 (although that was just about SHL), we can merge the guaranteed top zero bits from the shifted value, and then, if a min shift amount is known, zero out the top bits as well. SHL tests / handling will be added in a follow up patch.
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 | llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll |
 | llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll |
 | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp |
Commit
fd42a4ac7a69adb92f87c7fa927509f177dcc6ca
by llvm-dev[X86][SSE] Add add(shl(and(x,c1),c2),c3) test case with non-uniform shift value As mentioned by @nikic on rGef5debac4302, we should merge the guaranteed top zero bits from the shifted value and min shift amount code so they can both set the high bits to zero.
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 | llvm/test/CodeGen/X86/combine-shl.ll |
Commit
d94d079a6a5b12156e4b818c8ba46eb143f335b9
by diogo.sampaio[ARM][Thumb2] Fix ADD/SUB invalid writes to SP Summary: This patch fixes pr23772 [ARM] r226200 can emit illegal thumb2 instruction: "sub sp, r12, #80". The violation was that SUB and ADD (reg, immediate) instructions can only write to SP if the source register is also SP. So the above instructions was unpredictable. To enforce that the instruction t2(ADD|SUB)ri does not write to SP we now enforce the destination register to be rGPR (That exclude PC and SP). Different than the ARM specification, that defines one instruction that can read from SP, and one that can't, here we inserted one that can't write to SP, and other that can only write to SP as to reuse most of the hard-coded size optimizations. When performing this change, it uncovered that emitting Thumb2 Reg plus Immediate could not emit all variants of ADD SP, SP #imm instructions before so it was refactored to be able to. (see test/CodeGen/Thumb2/mve-stacksplot.mir where we use a subw sp, sp, Imm12 variant ) It also uncovered a disassembly issue of adr.w instructions, that were only written as SUBW instructions (see llvm/test/MC/Disassembler/ARM/thumb2.txt). Reviewers: eli.friedman, dmgreen, carwil, olista01, efriedma, andreadb Reviewed By: efriedma Subscribers: gbedwell, john.brawn, efriedma, ostannard, kristof.beyls, hiraditya, dmgreen, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70680
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 | llvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir |
 | llvm/test/MC/ARM/negative-immediates.s |
 | llvm/test/tools/llvm-mca/ARM/simple-cortex-m33.s |
 | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp |
 | llvm/lib/Target/ARM/Thumb2InstrInfo.cpp |
 | llvm/test/MC/ARM/basic-thumb2-instructions.s |
 | llvm/test/CodeGen/ARM/GlobalISel/thumb-select-arithmetic-ops.mir |
 | llvm/test/CodeGen/Thumb2/t2peephole-t2ADDrr-to-t2ADDri.ll |
 | llvm/test/MC/ARM/register-token-source-loc.s |
 | llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp |
 | llvm/lib/Target/ARM/ARMAsmPrinter.cpp |
 | llvm/test/MC/ARM/thumb-diagnostics.s |
 | llvm/test/CodeGen/Thumb2/peephole-cmp.mir |
 | llvm/test/CodeGen/Thumb2/peephole-addsub.mir |
 | llvm/test/MC/Disassembler/ARM/thumb2-v8.txt |
 | llvm/test/MC/Disassembler/ARM/thumb-tests.txt |
 | llvm/test/CodeGen/Thumb2/fp16-stacksplot.mir |
 | llvm/test/CodeGen/Thumb2/bug-subw.ll |
 | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp |
 | llvm/test/CodeGen/Thumb2/mve-stacksplot.mir |
 | llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp |
 | llvm/test/MC/Disassembler/ARM/thumb2.txt |
 | llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir |
 | llvm/test/MC/ARM/invalid-addsub.s |
 | llvm/lib/Target/ARM/ARMInstrThumb2.td |
 | llvm/test/MC/Disassembler/ARM/invalid-thumbv7.txt |
Commit
bad6032bc15fa8d16b67b86ef2b2fe48724e756e
by sam.parker[ARM][LowOverheadLoops] Change predicate inspection Use the already provided helper function to get the operand type so that we can detect whether the vpr is being used as a predicate or not. Also use existing helpers to get the predicate indices when we converting the vpt blocks. This enables us to support both types of vpr predicate operand. Differential Revision: https://reviews.llvm.org/D72504
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 | llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp |
 | llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmaxmin_vpred_r.mir |
Commit
c05a11108b9a9deb266c3c1758677462df61e05e
by llvm-dev[SelectionDAG] ComputeKnownBits - merge getValidMinimumShiftAmountConstant() and generic ISD::SHL handling. As mentioned by @nikic on rGef5debac4302, we can merge the guaranteed bottom zero bits from the shifted value, and then, if a min shift amount is known, zero out the bottom bits as well.
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 | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp |
 | llvm/test/CodeGen/X86/combine-shl.ll |
Commit
31aed2e0dad25d43039a9b933b1b95fbdeb27704
by llvm-devFix "MIParser::getIRValue(unsigned int)’ defined but not used" warning. NFCI.
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 | llvm/lib/CodeGen/MIRParser/MIParser.cpp |
Commit
e27632c3026328e41b0d7dbf25631041e979a2f9
by sam.parker[ARM][LowOverheadLoops] Allow all MVE instrs. We have a whitelist of instructions that we allow when tail predicating, since these are trivial ones that we've deemed need no special handling. Now change ARMLowOverheadLoops to allow the non-trivial instructions if they're contained within a valid VPT block. Since a valid block is one that is predicated upon the VCTP so we know that these non-trivial instructions will still behave as expected once the implicit predication is used instead. This also fixes a previous test failure. Differential Revision: https://reviews.llvm.org/D72509
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 | llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir |
 | llvm/unittests/Target/ARM/MachineInstrTest.cpp |
 | llvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir |
 | llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp |
Commit
877723b7ce813d25fc4a358b7d2cb90468733a72
by medismail.bennani[lldb/Expression] Improve interpreter error message with a non-running target When trying to interpret an expression with a function call, if the process hasn't been launched, the expression fails to be interpreted and the user gets the following error message: ```error: Can't run the expression locally``` This message doesn't explain why the expression failed to be interpreted, that's why this patch improves the error message that is displayed when trying to run an expression while no process is running. rdar://11991708 Differential Revision: https://reviews.llvm.org/D72510 Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
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 | lldb/packages/Python/lldbsuite/test/commands/expression/dont_allow_jit/TestAllowJIT.py |
 | lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp |
Commit
71d5454b377239213874a0d762860e6a3e60bf54
by simon.tatham[ARM,MVE] Use the new Tablegen `defvar` and `if` statements. Summary: This cleans up a lot of ugly `foreach` bodges that I've been using to work around the lack of those two language features. Now they both exist, I can make then all into something more legible! In particular, in the common pattern in `ARMInstrMVE.td` where a multiclass defines an `Instruction` instance plus one or more `Pat` that select it, I've used a `defvar` to wrap `!cast<Instruction>(NAME)` so that the patterns themselves become a little more legible. Replacing a `foreach` with a `defvar` removes a level of block structure, so several pieces of code have their indentation changed by this patch. Best viewed with whitespace ignored. NFC: the output of `llvm-tblgen -print-records` on the two affected Tablegen sources is exactly identical before and after this change, so there should be no effect at all on any of the other generated files. Reviewers: MarkMurrayARM, miyuki Reviewed By: MarkMurrayARM Subscribers: kristof.beyls, hiraditya, dmgreen, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D72690
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 | clang/include/clang/Basic/arm_mve.td |
 | llvm/lib/Target/ARM/ARMInstrMVE.td |
Commit
bff33bd5c83b947cccb4d6cf6ebca9dc021f716b
by Milos.Stojanovic[unittests] Fix "comparison of integers of different signs" warnings A warning is sent because `std::distance()` returns a signed type so `CmpHelperEQ()` gets instantiated into a function that compares differently signed arguments. Differential Revision: https://reviews.llvm.org/D72632
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 | llvm/unittests/ExecutionEngine/JITLink/LinkGraphTests.cpp |
 | llvm/unittests/Object/MinidumpTest.cpp |