Changes

[MLIR] Fix broken link locations after move to monorepo
I used the codemod python tool to do this with the following commands:
codemod 'tensorflow/mlir/blob/master/include'
'llvm/llvm-project/blob/master/mlir/include' codemod
'tensorflow/mlir/blob/master' 'llvm/llvm-project/blob/master/mlir' 
codemod 'tensorflow/mlir' 'llvm-project/llvm'
Differential Revision: https://reviews.llvm.org/D72244

[PowerPC] [NFC] set instruction number as 1st priority of lsr cost
model.

[MC] Don't resolve relocations referencing STB_LOCAL STT_GNU_IFUNC

[ELF] Add -z force-ibt and -z shstk for Intel Control-flow Enforcement
Technology
This patch is a joint work by Rui Ueyama and me based on D58102 by Xiang
Zhang.
It adds Intel CET (Control-flow Enforcement Technology) support to lld. 
The implementation follows the draft version of psABI which you can 
download from https://github.com/hjl-tools/x86-psABI/wiki/X86-psABI.
CET introduces a new restriction on indirect jump instructions so that 
you can limit the places to which you can jump to using indirect jumps.
In order to use the feature, you need to compile source files with
-fcf-protection=full.
* IBT is enabled if all input files are compiled with the flag. To force
enabling ibt, pass -z force-ibt.
* SHSTK is enabled if all input files are compiled with the flag, or if
-z shstk is specified.
IBT-enabled executables/shared objects have two PLT sections, ".plt" and
".plt.sec".  For the details as to why we have two sections, please read 
the comments.
Reviewed By: xiangzhangllvm
Differential Revision: https://reviews.llvm.org/D59780

[OpenMP][Tool] Make tests for archer dependent on TSan
If the openmp project is built standalone, the test compiler is feature
tested for an available -fsanitize=thread flag. If the openmp project is
built as part of llvm, the target tsan is needed to test archer.
An additional line (requires tsan) was introduced to the tests, this
patch updates the line numbers for the race.
Follow-up for 77ad98c
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D71914

[ELF] Delete unintended --force-bti

[OpenMP][Tool] Improving stack trace for Archer
The OpenMP runtime is not instrumented, so entering the runtime leaves
no hint on the source line of the pragma on ThreadSanitizer's function
stack.
This patch adds function entry/exit annotations for OpenMP parallel
regions, and synchronization regions (barrier, taskwait, taskgroup).
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D70408

[AMDGPU] Add gfx9 assembler and disassembler test cases
Summary: This adds assembler tests for cases that were previously only
in the disassembler tests, and vice versa.
Reviewers: rampitec, arsenm, nhaehnle
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye,
jfb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72592

[AMDGPU] Improve error checking in gfx10 assembler tests
Summary: This adds checks that the expected error was actually reported
against the correct instruction, and fixes a couple of problems that
that showed up: one incorrect W32-ERR:
 v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: error: invalid operand for instruction
+// W32-ERR: error: {{instruction not supported on this GPU|invalid
operand for instruction}}
and one missing W32-ERR:
 v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: error: invalid operand for instruction
Reviewers: rampitec, arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr,
t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72611

[AMDGPU] Remove duplicate gfx10 assembler and disassembler tests
Summary: Depends on D72611.
Reviewers: rampitec, arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr,
t-tye, jfb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72616

[lldb] Fix that SBThread.GetStopDescription is returning strings with
uninitialized memory at the end.
Summary:
`SBThread.GetStopDescription` is a curious API as it takes a buffer
length as a parameter that specifies how many bytes the buffer we pass
has. Then we fill the buffer until the specified length (or the length 
of the stop description string) and return the string length. If the
buffer is a nullptr however, we instead return how many bytes we would
have written to the buffer so that the user can allocate a buffer with 
the right size and pass that size to a subsequent
`SBThread.GetStopDescription` call.
Funnily enough, it is not possible to pass a nullptr via the Python SWIG
bindings, so that might be the first API in LLDB that is not only hard
to use correctly but impossible to use correctly. The only way to call
this function via Python is to throw in a large size limit that is
hopefully large enough to contain the stop description (otherwise we
only get the truncated stop description).
Currently passing a size limit that is smaller than the returned stop
description doesn't cause the Python bindings to return the stop
description but instead the truncated stop description + uninitialized
characters at the end of the string. The reason for this is that we
return the result of `snprintf` from the method which returns the amount
of bytes that *would* have been written (which is larger than the
buffer). This causes our Python bindings to return a string that is as
large as full stop description but the buffer that has been filled is
only as large as the passed in buffer size.
This patch fixes this issue by just recalculating the string length in
our buffer instead of relying on the wrong return value. We also have to
do this in a new type map as the old type map is also used for all
methods with the given argument pair `char *dst, size_t dst_len` (e.g.
SBProcess.GetSTDOUT`). These methods have different semantics for these
arguments and don't null-terminate the returned buffer (they instead
return the size in bytes) so we can't change the existing typemap
without breaking them.
Reviewers: labath, jingham
Reviewed By: labath
Subscribers: clayborg, shafik, abidh, JDevlieghere, lldb-commits
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D72086

[lldb] Don't defend against internal LLVM errors in IRInterpreter
Summary: Whenever we cast an LLVM instruction to one of its subclasses,
we do a double check if the RTTI enum value actually allows us to cast
the class. I don't see a way this can ever happen as even when LLVM's
RTTI system has some corrupt internal state (which we probably should
not test in the first place) we just reuse LLVM RTTI to do the second
check.
This also means that if we ever make an actual programming error in this
function (e.g., have a enum value and then cast it to a different
subclass), we just silently fall back to the JIT in our tests.
We also can't test this code in any reasonable way.
This removes the checks and uses `llvm::cast` instead which will raise a
fatal error when casting fails.
Reviewers: labath, mib
Reviewed By: labath
Subscribers: abidh, JDevlieghere, lldb-commits
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D72596

[mlir] Fix -Wunused

[AMDGPU] Fix getInstrLatency() always returning 1
We do not have InstrItinerary so generic getInstLatency() was always 
defaulting to return 1 cycle. We need to use TargetSchedModel instead to
compute an instruction's latency.
Differential Revision: https://reviews.llvm.org/D72655

[lldb][NFC] Rewrite python_api/rdar-12481949 test
Summary: This renames the test `rdar-12481949` to `get-value-32bit-int`
as it just tests that we return the correct result get calling
GetValueAsSigned/GetValueAsUnsigned on 32-bit integers.
It also deletes all the strange things going on in this test including
resetting the data formatters (which are to my knowledge not used to
calculate scalar values) and testing Python's long integers (let's just
assume that our Python distribution works correctly). Also modernises
the setup code.
Reviewers: labath, aprantl
Reviewed By: aprantl
Subscribers: JDevlieghere, lldb-commits
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D72593

[libcxx] [test] Add casts to avoid signed/unsigned mismatch warnings on
MSVC++
A bug was filed that these warnings should not be emitted as
DevCom-883961. (
https://developercommunity.visualstudio.com/content/problem/883961/c4389-signedunsigned-mismatch-should-not-be-emitte.html
)

[AMDGPU] Model distance to instruction in bundle
This change allows to model the height of the instruction within a
bundle for latency adjustment purposes.
Differential Revision: https://reviews.llvm.org/D72669

[llvm-readobj][test] - Fix grammar in comments.
This addresses post commit review comments for D71766.

[clang-tidy] Ignore implicit casts in modernize-use-default-member-init
Summary: Initialising a pointer from nullptr involves an implicit cast. 
Ignore it after getting initialiser from InitListExpr.
Fixes: PR44440
Reviewers: aaron.ballman, alexfh, JonasToth
Reviewed By: JonasToth
Subscribers: xazax.hun, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72630

[TableGen] Introduce a `defvar` statement.
Summary: This allows you to define a global or local variable to an
arbitrary value, and refer to it in subsequent definitions.
The main use I anticipate for this is if you have to compute some 
difficult function of the parameters of a multiclass, and then use it 
many times. For example:
  multiclass Foo<int i, string s> {
   defvar op = !cast<BaseClass>("whatnot_" # s # "_" # i);
   def myRecord {
     dag a = (op this, (op that, the other), (op x, y, z));
     int b = op.subfield;
   }
   def myOtherRecord<"template params including", op>;
 }
There are a couple of ways to do this already, but they're not really 
satisfactory. You can replace `defvar x = y` with a loop over a 
singleton list, `foreach x = [y] in { ... }` - but that's unintuitive to
someone who hasn't seen that workaround idiom before, and requires an
extra pair of braces that you often didn't really want. Or you can 
define a nested pair of multiclasses, with the inner one taking `x` as a
template parameter, and the outer one instantiating it just once with
the desired value of `x` computed from its other parameters - but that
makes it awkward to sequentially compute each value based on the 
previous ones. I think `defvar` makes things considerably easier.
You can also use `defvar` at the top level, where it inserts globals 
into the same map used by `defset`. That allows you to define global 
constants without having to make a dummy record for them to live in:
  defvar MAX_BUFSIZE = 512;
  // previously:
 // def Dummy { int MAX_BUFSIZE = 512; }
 // and then refer to Dummy.MAX_BUFSIZE everywhere
Reviewers: nhaehnle, hfinkel
Reviewed By: hfinkel
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71407

[TableGen] Introduce an if/then/else statement.
Summary: This allows you to make some of the defs in a multiclass or
`foreach` conditional on an expression computed from the parameters or
iteration variables.
It was already possible to simulate an if statement using a `foreach` 
with a dummy iteration variable and a list constructed using `!if` so 
that it had length 0 or 1 depending on the condition, e.g.
  foreach unusedIterationVar = !if(condition, [1], []<int>) in { ... }
But this syntax is nicer to read, and also more convenient because it 
allows an else clause.
To avoid upheaval in the implementation, I've implemented `if` as pure 
syntactic sugar on the `foreach` implementation: internally, `ParseIf` 
actually does construct exactly the kind of foreach shown above (and 
another reversed one for the else clause if present).
Reviewers: nhaehnle, hfinkel
Reviewed By: hfinkel
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71474

[Target] Fix uninitialized value in
10c11e4e2d05cf0e8f8251f50d84ce77eb1e9b8d

[ARM][MVE] Masked gathers from base + vector of offsets
Enables the masked gather pass to create a masked gather loading from a
base and vector of offsets. This also enables v8i16 and v16i8 gather
loads.
Differential Revision: https://reviews.llvm.org/D72330

[mlir] Add loop.parallel, loop.reduce and loop.reduce.return operations.
Summary: These operations can be used to specify a loop nest with a body
that can contain reductions. The iteration space can be iterated in any
order.
RFC:
https://groups.google.com/a/tensorflow.org/d/topic/mlir/pwtSgiKFPis/discussion
Differential Revision: https://reviews.llvm.org/D72394

[mlir] Ran git-clang-format.
Summary: I forgot to ran git-clang-format before committing.

[lldb][NFC] Cleanup ClangASTContext::CompleteTagDeclarationDefinition
Makes this function exit early instead of nesting if statements.
Also removed all the if (tag_type->getDecl()) checks. If we created a
TagType with a nullptr as a Decl then Clang would have already 
deferenced that nullptr during TagType creation so there is no point in
gracefully handling a nullptr here.

[mlir] Create a gpu.module operation for the GPU Dialect.
Summary: This is based on the use of code constantly checking for an
attribute on a model and instead represents the distinct operaion with a
different op. Instead, this op can be used to provide better filtering.
Reviewers: herhut, mravishankar, antiagainst, rriddle
Reviewed By: herhut, antiagainst, rriddle
Subscribers: liufengdb, aartbik, jholewinski, mgorny, mehdi_amini,
rriddle, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache,
csigg, arpith-jacob, mgester, lucyrfox, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72336

[RISCV] Fix ILP32D lowering for double+double/double+int return types
Summary: Previously, since these aggregates are > 2*XLen, Clang would
think they were being returned indirectly and thus would decrease the
number of available GPRs available by 1. For long argument lists this
could lead to a struct argument incorrectly being passed indirectly.
Reviewers: asb, lenary
Reviewed By: asb, lenary
Subscribers: luismarques, rbar, johnrusso, simoncook, apazos, sabuasal,
niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01,
MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna,
Jim, lenary, s.egerton, pzheng, sameer.abuasal, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D69590

[mlir] Fix translation of splat constants to LLVM IR
Summary: When converting splat constants for nested sequential LLVM IR
types wrapped in MLIR, the constant conversion was erroneously assuming
it was always possible to recursively construct a constant of a
sequential type given only one value. Instead, wait until all sequential
types are unpacked recursively before constructing a scalar constant and
wrapping it into the surrounding sequential type.
Subscribers: mehdi_amini, rriddle, jpienaar, burmako, shauheen,
antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, aartbik,
liufengdb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72688

[ARM][MVE] Disallow VPSEL for tail predication
Due to the current way that we collect predicated instructions, we can't
easily handle vpsel in tail predicated loops. There are a couple of
issues: 1) It will use the VPR as a predicate operand, but doesn't have
to be
  instead a VPT block, which means we can assert while building up
  the VPT block because we don't find another VPST to being a new
  one. 2) VPSEL still requires a VPR operand even after tail
predicating,
  which means we can't remove it unless there is another
  instruction, such as vcmp, that can provide the VPR def.
The first issue should be a relatively simple fix in the logic of the 
LowOverheadLoops pass, whereas the second will require us to represent
the 'implicit' tail predication with an explicit value.
Differential Revision: https://reviews.llvm.org/D72629

[SelectionDAG] ComputeKnownBits - merge
getValidMinimumShiftAmountConstant() and generic ISD::SRL handling.
As mentioned by @nikic on rGef5debac4302 (although that was just about
SHL), we can merge the guaranteed top zero bits from the shifted value,
and then, if a min shift amount is known, zero out the top bits as well.
SHL tests / handling will be added in a follow up patch.

[X86][SSE] Add add(shl(and(x,c1),c2),c3) test case with non-uniform
shift value
As mentioned by @nikic on rGef5debac4302, we should merge the guaranteed
top zero bits from the shifted value and min shift amount code so they
can both set the high bits to zero.

[ARM][Thumb2] Fix ADD/SUB invalid writes to SP
Summary: This patch fixes pr23772  [ARM] r226200 can emit illegal thumb2
instruction: "sub sp, r12, #80". The violation was that SUB and ADD
(reg, immediate) instructions can only write to SP if the source
register is also SP. So the above instructions was unpredictable. To
enforce that the instruction t2(ADD|SUB)ri does not write to SP we now
enforce the destination register to be rGPR (That exclude PC and SP). 
Different than the ARM specification, that defines one instruction that
can read from SP, and one that can't, here we inserted one that can't
write to SP, and other that can only write to SP as to reuse most of the
hard-coded size optimizations. When performing this change, it uncovered
that emitting Thumb2 Reg plus Immediate could not emit all variants of
ADD SP, SP #imm instructions before so it was refactored to be able to.
(see test/CodeGen/Thumb2/mve-stacksplot.mir where we use a subw sp, sp,
Imm12 variant ) It also uncovered a disassembly issue of adr.w
instructions, that were only written as SUBW instructions (see
llvm/test/MC/Disassembler/ARM/thumb2.txt).
Reviewers: eli.friedman, dmgreen, carwil, olista01, efriedma, andreadb
Reviewed By: efriedma
Subscribers: gbedwell, john.brawn, efriedma, ostannard, kristof.beyls,
hiraditya, dmgreen, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70680

[ARM][LowOverheadLoops] Change predicate inspection
Use the already provided helper function to get the operand type so that
we can detect whether the vpr is being used as a predicate or not. Also
use existing helpers to get the predicate indices when we converting the
vpt blocks. This enables us to support both types of vpr predicate
operand.
Differential Revision: https://reviews.llvm.org/D72504

[SelectionDAG] ComputeKnownBits - merge
getValidMinimumShiftAmountConstant() and generic ISD::SHL handling.
As mentioned by @nikic on rGef5debac4302, we can merge the guaranteed
bottom zero bits from the shifted value, and then, if a min shift amount
is known, zero out the bottom bits as well.

Fix "MIParser::getIRValue(unsigned int)’ defined but not used" warning.
NFCI.

[ARM][LowOverheadLoops] Allow all MVE instrs.
We have a whitelist of instructions that we allow when tail predicating,
since these are trivial ones that we've deemed need no special handling.
Now change ARMLowOverheadLoops to allow the non-trivial instructions if
they're contained within a valid VPT block. Since a valid block is one
that is predicated upon the VCTP so we know that these non-trivial
instructions will still behave as expected once the implicit predication
is used instead.
This also fixes a previous test failure.
Differential Revision: https://reviews.llvm.org/D72509

[lldb/Expression] Improve interpreter error message with a non-running
target
When trying to interpret an expression with a function call, if the 
process hasn't been launched, the expression fails to be interpreted and
the user gets the following  error message:
```error: Can't run the expression locally```
This message doesn't explain why the expression failed to be 
interpreted, that's why this patch improves the error message that is 
displayed when trying to run an expression while no process is running.
rdar://11991708
Differential Revision: https://reviews.llvm.org/D72510
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>

[ARM,MVE] Use the new Tablegen `defvar` and `if` statements.
Summary: This cleans up a lot of ugly `foreach` bodges that I've been
using to work around the lack of those two language features. Now they
both exist, I can make then all into something more legible!
In particular, in the common pattern in `ARMInstrMVE.td` where a 
multiclass defines an `Instruction` instance plus one or more `Pat` that 
select it, I've used a `defvar` to wrap `!cast<Instruction>(NAME)` so 
that the patterns themselves become a little more legible.
Replacing a `foreach` with a `defvar` removes a level of block 
structure, so several pieces of code have their indentation changed by 
this patch. Best viewed with whitespace ignored.
NFC: the output of `llvm-tblgen -print-records` on the two affected 
Tablegen sources is exactly identical before and after this change, so 
there should be no effect at all on any of the other generated files.
Reviewers: MarkMurrayARM, miyuki
Reviewed By: MarkMurrayARM
Subscribers: kristof.beyls, hiraditya, dmgreen, cfe-commits,
llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D72690

[unittests] Fix "comparison of integers of different signs" warnings
A warning is sent because `std::distance()` returns a signed type so
`CmpHelperEQ()` gets instantiated into a function that compares 
differently signed arguments.
Differential Revision: https://reviews.llvm.org/D72632