FailedChanges

Summary

  1. [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in (details)
  2. [libcxx testing] Fix -Wtautological-overlap-compare bug (details)
  3. [ARM,MVE] Use VMOV.{S8,S16} for sign-extended extractelement. (details)
  4. [AArch64][SVE] Allocate locals that are scalable vectors. (details)
  5. [InstCombine] Fold PHIs with equal incoming pointers (details)
  6. [AArch64] Extend storeRegToStackSlot to spill SVE registers. (details)
  7. [DebugInfo] Add helper for finding entry value candidates [NFC] (details)
  8. [DebugInfo] Avoid creating entry values for clobbered registers (details)
  9. Temporarily revert "[InstCombine] Fold PHIs with equal incoming (details)
  10. [OpenCL] Add remaining vector data builtin functions (details)
  11. [mips][test] Add Mips CPU tests. NFC (details)
  12. [mips] Show an error if 64-bit target triple provided with 32-bit CPU (details)
  13. [Mips] Add rematerialization support for ldi.fmt (details)
Commit d384ad6b636d4a8c55ef53d5316d008a05161b1f by joan.lluch
[TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in
DAGCombine (4)
Summary: Replaces
``` unsigned getShiftAmountThreshold(EVT VT)
``` by
``` bool shouldAvoidTransformToShift(EVT VT, unsigned amount)
``` thus giving more flexibility for targets to decide whether
particular shift amounts must be considered expensive or not.
Updates the MSP430 target with a custom implementation.
This continues  D69116, D69120, D69326 and updates them, so all of them
must be committed before this.
Existing tests apply, a few more have been added.
Reviewers: asl, spatel
Reviewed By: spatel
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70042
The file was modifiedllvm/lib/Target/MSP430/MSP430ISelLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/lib/Target/MSP430/MSP430ISelLowering.h
The file was modifiedllvm/test/CodeGen/MSP430/shift-amount-threshold.ll
Commit 1d55c9e59ebf3f3ff572d42da433b2f72f1ce900 by dave
[libcxx testing] Fix -Wtautological-overlap-compare bug
The file was modifiedlibcxx/test/support/container_debug_tests.h
Commit 5b9e4daef06dcfefc786737a32c8bbb5bd0fc5c4 by simon.tatham
[ARM,MVE] Use VMOV.{S8,S16} for sign-extended extractelement.
MVE includes instructions that extract an 8- or 16-bit lane from a
vector and sign-extend it into the output 32-bit GPR. `ARMInstrMVE.td`
already included isel patterns to select those instructions in response
to the `ARMISD::VGETLANEs` selection-DAG node type. But
`ARMISD::VGETLANEs` was never actually generated, because the code that
creates it was conditioned on NEON only.
It's an easy fix to enable the same code for integer MVE, and now IR
that sign-extends the result of an extractelement (whether explicitly or
as part of the function call ABI) will use `vmov.s8` instead of
`vmov.u8` followed by `sxtb`.
Reviewers: SjoerdMeijer, dmgreen, ostannard
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70132
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was addedllvm/test/CodeGen/Thumb2/mve-extractelt.ll
Commit 9a1c243aa5ded10f7b39887b2be073d0bcfbf5c9 by sander.desmalen
[AArch64][SVE] Allocate locals that are scalable vectors.
This patch adds a target interface to set the StackID for a given type,
which allows scalable vectors (e.g. `<vscale x 16 x i8>`) to be assigned
a
'sve-vec' StackID, so it is allocated in the SVE area of the stack
frame.
Reviewers: ostannard, efriedma, rengolin, cameron.mcinally
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D70080
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetFrameLowering.h
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.h
The file was modifiedllvm/test/CodeGen/AArch64/framelayout-sve.mir
The file was modifiedllvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
The file was addedllvm/test/CodeGen/AArch64/sve-alloca-stackid.ll
Commit bbb29738b58aaf6f6518269abdcf8f64131665a9 by suc-daniil
[InstCombine] Fold PHIs with equal incoming pointers
In case when all incoming values of a PHI are equal pointers, this
transformation inserts a definition of such a pointer right after
definition of the base pointer and replaces with this value both PHI and
all it's incoming pointers. Primary goal of this transformation is
canonicalization of this pattern in order to enable optimizations that
can't handle PHIs. Non-inbounds pointers aren't currently supported.
Reviewers: spatel, RKSimon, lebedev.ri, apilipenko
Reviewed By: apilipenko
Tags: #llvm
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D68128
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineInternal.h
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombinePHI.cpp
The file was modifiedllvm/test/Transforms/InstCombine/phi-equal-incoming-pointers.ll
Commit 3367686b4d126e8e035c618829c78315f7751dfd by sander.desmalen
[AArch64] Extend storeRegToStackSlot to spill SVE registers.
This patch allows the register allocator to spill SVE registers to the
stack.
Reviewers: ostannard, efriedma, rengolin, cameron.mcinally
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D70082
The file was addedllvm/test/CodeGen/AArch64/spillfill-sve.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
Commit 4fec44cd61517cda16f94067a34982628bda34f7 by david.stenberg
[DebugInfo] Add helper for finding entry value candidates [NFC]
Summary: The conditions that are used to determine if entry values
should be emitted for a parameter are quite many, and will grow slightly
in a follow-up commit, so move those to a helper function, as was
suggested in the code review for D69889.
Reviewers: djtodoro, NikolaPrica
Reviewed By: djtodoro
Subscribers: probinson, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69955
The file was modifiedllvm/lib/CodeGen/LiveDebugValues.cpp
Commit 5e646ff53052c5d8694f2da14b9a094202fee729 by david.stenberg
[DebugInfo] Avoid creating entry values for clobbered registers
Summary: Entry values are considered for parameters that have
register-described DBG_VALUEs in the entry block (along with other
conditions).
If a parameter's value has been propagated from the caller to the
callee, then the parameter's DBG_VALUE in the entry block may be
described using a register defined by some instruction, and entry values
should not be emitted for the parameter, which can currently occur. One
such case was seen in the attached test case, in which the second
parameter, which is described by a redefinition of the first parameter's
register, would incorrectly get an entry value using the first
parameter's register. This commit intends to solve such cases by keeping
track of register defines, and ignoring DBG_VALUEs in the entry block
that are described by such registers.
In a RelWithDebInfo build of clang-8, the average size of the set was
27, and in a RelWithDebInfo+ASan build it was 30.
Reviewers: djtodoro, NikolaPrica, aprantl, vsk
Reviewed By: djtodoro, vsk
Subscribers: hiraditya, llvm-commits
Tags: #debug-info, #llvm
Differential Revision: https://reviews.llvm.org/D69889
The file was modifiedllvm/lib/CodeGen/LiveDebugValues.cpp
The file was addedllvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir
Commit cba4a27745ab33b828476eff47caf3e1b6e060f5 by suc-daniil
Temporarily revert "[InstCombine] Fold PHIs with equal incoming
pointers"
Revert due to sanitizer-windows buildbot failure.
This reverts commit bbb29738b58aaf6f6518269abdcf8f64131665a9.
The file was modifiedllvm/test/Transforms/InstCombine/phi-equal-incoming-pointers.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombinePHI.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineInternal.h
Commit 2fe674baa3f304b5fa497e71b51ea6315f89c5e0 by sven.vanhaastregt
[OpenCL] Add remaining vector data builtin functions
Add the remaining half (fp16) vector data load and store builtin
functions from the OpenCL C specification.
Patch by Pierre Gondois and Sven van Haastregt.
The file was modifiedclang/lib/Sema/OpenCLBuiltins.td
Commit b3853d852629d1a2713cf47a2422c46c0c630f87 by simon
[mips][test] Add Mips CPU tests. NFC
Adding tests check all available CPUs on Mips.
Patch by Miloš Stojanović.
Differential Revision: https://reviews.llvm.org/D70017
The file was addedllvm/test/CodeGen/Mips/cpus.ll
Commit 068db2ed4d1879e100fb12f2a3d75e38b8867b46 by simon
[mips] Show an error if 64-bit target triple provided with 32-bit CPU
When a 64-bit triple is used emit an error if the CPU only supports
32-bit code.
Patch by Miloš Stojanović.
Differential Revision: https://reviews.llvm.org/D70018
The file was addedllvm/test/CodeGen/Mips/cpus-no-mips64.ll
The file was modifiedllvm/lib/Target/Mips/MipsSubtarget.cpp
Commit fed17867cd42c5fa8a7a561637d539fbde6f511f by Mirko.Brkusanin
[Mips] Add rematerialization support for ldi.fmt
Instruction ldi.fmt can be considered cheap enough to avoid spill and
restore of value that it produces since it's loaded from immediate.
Differential Revision: https://reviews.llvm.org/D69898
The file was addedllvm/test/CodeGen/Mips/msa/remat-ldi.ll
The file was modifiedllvm/lib/Target/Mips/MipsMSAInstrInfo.td