SuccessChanges

Summary

  1. [ARM] MVE i1 splat (details)
  2. Revert r372285 "GlobalISel: Don't materialize immarg arguments to (details)
  3. [DAG] Add SelectionDAG::MaxRecursionDepth constant (details)
  4. [clang-tidy] Fix bugprone-argument-comment-check to correctly ignore (details)
  5. [CUDA][HIP] Fix typo in `BestViableFunction` (details)
  6. Clean out unused diagnostics. NFC. (details)
  7. [TableGen] Support encoding per-HwMode (details)
  8. [OpenCL] Add version handling and add vector ld/st builtins (details)
  9. Remove an unsafe member variable that wasn't needed; NFC. (details)
  10. [Float2Int] auto-generate complete test checks; NFC (details)
  11. Reverting r372323 because it broke color tests on Linux. (details)
  12. [docs] Break long (>80) line. NFC (details)
  13. [DAGCombiner] Add node to the worklist in topological order in (details)
  14. [DAG][X86] Convert isNegatibleForFree/GetNegatedExpression to a target (details)
  15. Revert r372325 - Reverting r372323 because it broke color tests on (details)
  16. X86: Add missing test for vshli SimplifyDemandedBitsForTargetNode (details)
  17. Make appendCallNB lambda mutable (details)
  18. [MCA] Improved cost computation for loop carried dependencies in the (details)
  19. Reapply r372285 "GlobalISel: Don't materialize immarg arguments to (details)
  20. [Float2Int] avoid crashing on unreachable code (PR38502) (details)
  21. [AMDGPU] Unnecessary -amdgpu-scalarize-global-loads=false flag removed (details)
  22. [InstCombine] Simplify @llvm.usub.with.overflow+non-zero check (PR43251) (details)
  23. [SVFS] Vector Function ABI demangling. (details)
  24. gn build: Merge r372343 (details)
  25. [NFC][PowerPC] Fast-isel VSX support test (details)
  26. [Analysis] Allow -scalar-evolution-max-iterations more than once (details)
  27. Don't use invalidated iterators in FlattenCFGPass (details)
  28. [lsan] Fix deadlock in dl_iterate_phdr. (details)
  29. llvm-reduce: Follow-up to 372280, now with more-better msan fixing (details)
  30. [AMDGPU] fixed underflow in getOccupancyWithNumVGPRs (details)
  31. Don't false-positive match against binary path. (details)
  32. [ObjC][ARC] Skip debug instructions when computing the insert point of (details)
  33. Revert "[CUDA][HIP] Fix typo in `BestViableFunction`" (details)
  34. [CUDA][HIP] Re-apply part of r372318. (details)
  35. [AArch64] Fix formatting (NFC) (details)
  36. [WebAssembly][NFC] Remove unnecessary braces (details)
  37. Model converted constant expressions as full-expressions. (details)
  38. Fix for stringized function-macro args continued across lines (details)
  39. [Consumed] Treat by-value class arguments as consuming by default, like (details)
  40. MachineScheduler: Fix missing dependency with multiple subreg defs (details)
  41. [NFCI] Always initialize const members of AttributeCommonInfo (details)
  42. Revert "Fix swig python package path" (details)
  43. [X86] Remove the special isBuildVectorOfConstantSDNodes handling from (details)
  44. Use getTargetConstant for BLENDI, and add a test to catch it. (details)
  45. llvm-undname: Delete an empty, unused method. (details)
  46. Finish building the full-expression for a static_assert expression (details)
  47. [Object] Uncapitalize an error message (details)
  48. [llvm-ar] Removes repetition in the error message (details)
  49. [X86] Use timm in MMX pinsrw/pextrw isel patterns. Add missing test (details)
  50. [llvm-readobj] flush output before crash (details)
  51. [X86] Convert tbm_bextri_u32/tbm_bextri_u64 intrinsics TargetConstant (details)
  52. Reapply [llvm-ar] Include a line number when failing to parse an MRI (details)
  53. [CallSiteSplitting] Remove unused includes (NFC). (details)
  54. [MachinePipeliner] Improve the TargetInstrInfo API (details)
  55. [yaml2obj/obj2yaml] - Do not trigger llvm_unreachable when (details)
  56. [llvm-dwarfdump] Adjust Windows path to be acceptable by JSON (details)
  57. [NFC] Test commit, deleting some whitespace (details)
  58. [IntrinsicEmitter] Add overloaded types for SVE intrinsics (Subdivide2 & (details)
  59. [lldb][NFC] Remove unused include in TestLineEntry.cpp (details)
  60. Revert r372366 "Use getTargetConstant for BLENDI, and add a test to (details)
  61. [AMDGPU] Use std::make_tuple to make some toolchains happy again (details)
Commit 0cfb78e52af247366e6e8fe00a906022bf4abca5 by david.green
[ARM] MVE i1 splat
We needn't BFI each lane individually into a predicate register when
each lane in the same. A simple sign extend and a vmsr will do.
Differential Revision: https://reviews.llvm.org/D67653
llvm-svn: 372313
The file was modifiedllvm/test/CodeGen/Thumb2/mve-pred-build-var.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit 13bdae8541c3fc5acf6ee7de78ec5ab8446848e4 by hans
Revert r372285 "GlobalISel: Don't materialize immarg arguments to
intrinsics"
This broke the Chromium build, causing it to fail with e.g.
  fatal error: error in backend: Cannot select: t362: v4i32 =
X86ISD::VSHLI t392, Constant:i8<15>
See llvm-commits thread of r372285 for details.
This also reverts r372286, r372287, r372288, r372289, r372290, r372291,
r372292, r372293, r372296, and r372297, which seemed to depend on the
main commit.
> Encode them directly as an imm argument to G_INTRINSIC*.
>
> Since now intrinsics can now define what parameters are required to be
> immediates, avoid using registers for them. Intrinsics could
> potentially want a constant that isn't a legal register type. Also,
> since G_CONSTANT is subject to CSE and legalization, transforms could
> potentially obscure the value (and create extra work for the
> selector). The register bank of a G_CONSTANT is also meaningful, so
> this could throw off future folding and legalization logic for AMDGPU.
>
> This will be much more convenient to work with than needing to call
> getConstantVRegVal and checking if it may have failed for every
> constant intrinsic parameter. AMDGPU has quite a lot of intrinsics wth
> immarg operands, many of which need inspection during lowering. Having
> to find the value in a register is going to add a lot of boilerplate
> and waste compile time.
>
> SelectionDAG has always provided TargetConstant for constants which
> should not be legalized or materialized in a register. The distinction
> between Constant and TargetConstant was somewhat fuzzy, and there was
> no automatic way to force usage of TargetConstant for certain
> intrinsic parameters. They were both ultimately ConstantSDNode, and it
> was inconsistently used. It was quite easy to mis-select an
> instruction requiring an immediate. For SelectionDAG, start emitting
> TargetConstant for these arguments, and using timm to match them.
>
> Most of the work here is to cleanup target handling of constants. Some
> targets process intrinsics through intermediate custom nodes, which
> need to preserve TargetConstant usage to match the intrinsic
> expectation. Pattern inputs now need to distinguish whether a constant
> is merely compatible with an operand or whether it is mandatory.
>
> The GlobalISelEmitter needs to treat timm as a special case of a leaf
> node, simlar to MachineBasicBlock operands. This should also enable
> handling of patterns for some G_* instructions with immediates, like
> G_FENCE or G_EXTRACT.
>
> This does include a workaround for a crash in GlobalISelEmitter when
> ARM tries to uses "imm" in an output with a "timm" pattern source.
llvm-svn: 372314
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was removedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
The file was removedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
The file was removedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrTSX.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
The file was modifiedllvm/lib/Target/X86/X86InstrAVX512.td
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrVSX.td
The file was modifiedllvm/lib/Target/X86/X86InstrSystem.td
The file was modifiedllvm/lib/Target/Hexagon/HexagonIntrinsics.td
The file was removedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
The file was removedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
The file was modifiedllvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
The file was modifiedllvm/lib/Target/ARM/ARMInstrInfo.td
The file was removedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
The file was modifiedllvm/lib/Target/X86/X86InstrXOP.td
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepOperands.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll
The file was removedllvm/test/TableGen/immarg.td
The file was modifiedllvm/lib/Target/Mips/MipsSEISelLowering.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZPatterns.td
The file was modifiedllvm/lib/Target/AMDGPU/BUFInstructions.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrAltivec.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll
The file was modifiedllvm/lib/Target/AMDGPU/DSInstructions.td
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrBulkMemory.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir
The file was modifiedllvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
The file was removedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
The file was modifiedllvm/lib/Target/ARM/ARMInstrThumb2.td
The file was removedllvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
The file was modifiedllvm/lib/Target/Mips/Mips64InstrInfo.td
The file was modifiedllvm/lib/Target/X86/X86InstrMMX.td
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/CodeGen/ScheduleDAGInstrs.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrSSE.td
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SOPInstructions.td
The file was modifiedllvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td
The file was removedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll
The file was modifiedllvm/lib/Target/Mips/MipsInstrInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/VOP1Instructions.td
The file was removedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.sleep.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was removedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
The file was removedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
The file was modifiedllvm/include/llvm/Target/TargetSelectionDAG.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
The file was modifiedllvm/lib/Target/Mips/MipsDSPInstrInfo.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrVector.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrFormats.td
The file was modifiedllvm/lib/Target/Mips/MipsMSAInstrInfo.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZOperands.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoA.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZOperators.td
Commit c65dd89804d35fbd6170b61a0d1494df0576d352 by llvm-dev
[DAG] Add SelectionDAG::MaxRecursionDepth constant
As commented on D67557 we have a lot of uses of depth checks all using
magic numbers.
This patch adds the SelectionDAG::MaxRecursionDepth constant and moves
over some general cases to use this explicitly.
Differential Revision: https://reviews.llvm.org/D67711
llvm-svn: 372315
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/include/llvm/CodeGen/SelectionDAG.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit 57990b4be0aa2d7aefd186ec2dd61ab705b4e426 by yitzhakm
[clang-tidy] Fix bugprone-argument-comment-check to correctly ignore
implicit constructors.
Summary: After revision 370919, this check incorrectly flags certain
cases of implicit constructors. Specifically, if an argument is
annotated with an argument-comment and the argument expression triggers
an implicit constructor, then the argument comment is associated with
argument of the implicit constructor.
However, this only happens when the constructor has more than one
argument. This revision fixes the check for implicit constructors and
adds a regression test for this case.
Note: r370919 didn't cause this bug, it simply uncovered it by fixing
another bug that was masking the behavior.
Reviewers: gribozavr
Subscribers: xazax.hun, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D67744
llvm-svn: 372317
The file was modifiedclang-tools-extra/test/clang-tidy/bugprone-argument-comment.cpp
The file was modifiedclang-tools-extra/clang-tidy/bugprone/ArgumentCommentCheck.cpp
Commit eb231d15825ac345b546f4c99372d1cac8f14f02 by michael.hliao
[CUDA][HIP] Fix typo in `BestViableFunction`
Summary:
- Should consider viable ones only when checking SameSide candidates.
- Replace erasing with clearing viable flag to reduce data
moving/copying.
- Add one and revise another one as the diagnostic message are more
relevant compared to previous one.
Reviewers: tra
Subscribers: cfe-commits, yaxunl
Tags: #clang
Differential Revision: https://reviews.llvm.org/D67730
llvm-svn: 372318
The file was modifiedclang/lib/Sema/SemaOverload.cpp
The file was modifiedclang/test/SemaCUDA/function-overload.cu
The file was modifiedclang/test/SemaCUDA/implicit-member-target-collision-cxx11.cu
Commit b88800d8829b9a6602547e26050fffd528e21822 by benny.kra
Clean out unused diagnostics. NFC.
llvm-svn: 372319
The file was modifiedclang/include/clang/Basic/DiagnosticFrontendKinds.td
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/include/clang/Basic/DiagnosticASTKinds.td
The file was modifiedclang/include/clang/Basic/DiagnosticCommonKinds.td
The file was modifiedclang/include/clang/Basic/DiagnosticDriverKinds.td
Commit 88a5fbfcea79b4711542f0587bed39aa392da12f by jmolloy
[TableGen] Support encoding per-HwMode
Much like ValueTypeByHwMode/RegInfoByHwMode, this patch allows targets
to modify an instruction's encoding based on HwMode. When the
EncodingInfos field is non-empty the Inst and Size fields of the
Instruction are ignored and taken from EncodingInfos instead.
As part of this promote getHwMode() from TargetSubtargetInfo to
MCSubtargetInfo.
This is NFC for all existing targets - new code is generated only if
targets use EncodingByHwMode.
llvm-svn: 372320
The file was modifiedllvm/utils/TableGen/CodeGenTarget.cpp
The file was modifiedllvm/utils/TableGen/InfoByHwMode.cpp
The file was modifiedllvm/utils/TableGen/CodeEmitterGen.cpp
The file was modifiedllvm/utils/TableGen/FixedLenDecoderEmitter.cpp
The file was modifiedllvm/utils/TableGen/SubtargetEmitter.cpp
The file was modifiedllvm/include/llvm/Target/Target.td
The file was modifiedllvm/include/llvm/CodeGen/TargetSubtargetInfo.h
The file was modifiedllvm/include/llvm/MC/MCSubtargetInfo.h
The file was addedllvm/test/TableGen/HwModeEncodeDecode.td
The file was modifiedllvm/utils/TableGen/InfoByHwMode.h
Commit ed69faa01bfff02c61e318ef4bfc4112fa87b1a0 by sven.vanhaastregt
[OpenCL] Add version handling and add vector ld/st builtins
Allow setting a MinVersion, stating from which OpenCL version a builtin
function is available, and a MaxVersion, stating from which OpenCL
version a builtin function should not be available anymore.
Guard some definitions of the "work-item" builtin functions according to
the OpenCL versions from which they are available.
Add the "vector data load and store" builtin functions (e.g.
vload/vstore), whose signatures differ before and after OpenCL 2.0 in
the pointer argument address spaces.
Patch by Pierre Gondois and Sven van Haastregt.
Differential Revision: https://reviews.llvm.org/D63504
llvm-svn: 372321
The file was modifiedclang/lib/Sema/OpenCLBuiltins.td
The file was modifiedclang/utils/TableGen/ClangOpenCLBuiltinEmitter.cpp
The file was modifiedclang/lib/Sema/SemaLookup.cpp
The file was modifiedclang/test/SemaOpenCL/fdeclare-opencl-builtins.cl
Commit 3c3602aefa5909291ce5e32a43b2effb08e4053a by aaron
Remove an unsafe member variable that wasn't needed; NFC.
People use the AST dumping interface while debugging, so it's not safe
to assume that a declaration will be dumped before a constant expression
is dumped. This means the Context member may not get set properly and
problems would happen. Rather than rely on the interface that requires
the ASTContext, call the generic dump() interface instead; this allows
us to remove the Context member variable.
llvm-svn: 372323
The file was modifiedclang/include/clang/AST/TextNodeDumper.h
The file was modifiedclang/lib/AST/TextNodeDumper.cpp
Commit 7592e3a81fc0045b48207531e42ec7cf8af60fbd by spatel
[Float2Int] auto-generate complete test checks; NFC
llvm-svn: 372324
The file was modifiedllvm/test/Transforms/Float2Int/basic.ll
Commit ed9104c3f8781ed6f5dc6e7d7034158d062c2510 by aaron
Reverting r372323 because it broke color tests on Linux.
http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/17919
llvm-svn: 372325
The file was modifiedclang/lib/AST/TextNodeDumper.cpp
The file was modifiedclang/include/clang/AST/TextNodeDumper.h
Commit cde4f727fffe4ea04ae95f831ba788781d2f20eb by francesco.petrogalli
[docs] Break long (>80) line. NFC
llvm-svn: 372326
The file was modifiedllvm/docs/Frontend/PerformanceTips.rst
Commit 9e94ef42bab003026a433687d9f44d8137f16d17 by deadalnix
[DAGCombiner] Add node to the worklist in topological order in
scalarizeExtractedVectorLoad
Summary: As per title.
Reviewers: craig.topper, efriedma, RKSimon, lebedev.ri
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D66661
llvm-svn: 372327
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit af6043557dd1478beff83c44b21dd07b5e322c15 by llvm-dev
[DAG][X86] Convert isNegatibleForFree/GetNegatedExpression to a target
hook (PR42863)
This patch converts the DAGCombine
isNegatibleForFree/GetNegatedExpression into overridable TLI hooks and
includes a demonstration X86 implementation.
The intention is to let us extend existing FNEG combines to work more
generally with negatible float ops, allowing it work with target
specific combines and opcodes (e.g. X86's FMA variants).
Unlike the SimplifyDemandedBits, we can't just handle target nodes
through a Target callback, we need to do this as an override to allow
targets to handle generic opcodes as well. This does mean that the
target implementations has to duplicate some checks (recursion depth
etc.).
I've only begun to replace X86's FNEG handling here, handling
FMADDSUB/FMSUBADD negation and some low impact codegen changes (some FMA
negatation propagation). We can build on this in future patches.
Differential Revision: https://reviews.llvm.org/D67557
llvm-svn: 372333
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.h
The file was modifiedllvm/test/CodeGen/X86/recip-fastmath.ll
The file was modifiedllvm/test/CodeGen/X86/recip-fastmath2.ll
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit efb9e45d6bc5dda4d3131701df24cf764e99d544 by aaron
Revert r372325 - Reverting r372323 because it broke color tests on
Linux.
This corrects the testing issues.
llvm-svn: 372334
The file was modifiedclang/lib/AST/TextNodeDumper.cpp
The file was modifiedclang/include/clang/AST/TextNodeDumper.h
The file was modifiedclang/test/AST/ast-dump-color.cpp
Commit 7decdbf2db8fcf78233f40195f6d5c5b7c396224 by Matthew.Arsenault
X86: Add missing test for vshli SimplifyDemandedBitsForTargetNode
This would have caught this regression which triggered the revert of
r372285: https://bugs.chromium.org/p/chromium/issues/detail?id=1005750
llvm-svn: 372335
The file was addedllvm/test/CodeGen/X86/vshli-simplify-demanded-bits.ll
Commit 7cb60fb00f545dae7e161d8b7c24d674d7d008f9 by chris.bieneman
Make appendCallNB lambda mutable
Lambdas are by deafult const so that they produce the same output every
time they are run. This lambda needs to set the value on a captured
promise which is a mutating operation, so it must be mutable.
llvm-svn: 372336
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/RPCUtils.h
Commit e0900f285bb532790ed494df901f87c5c8b904da by Andrea_DiBiagio
[MCA] Improved cost computation for loop carried dependencies in the
bottleneck analysis.
This patch introduces a cut-off threshold for dependency edge frequences
with the goal of simplifying the critical sequence computation.  This
patch also removes the cost normalization for loop carried dependencies.
We didn't really need to artificially amplify the cost of loop-carried
dependencies since it is already computed as the integral over time of
the delay (in cycle).
In the absence of backend stalls there is no need for computing a
critical sequence. With this patch we early exit from the critical
sequence computation if no bottleneck was reported during the
simulation.
llvm-svn: 372337
The file was modifiedllvm/tools/llvm-mca/Views/BottleneckAnalysis.h
The file was modifiedllvm/tools/llvm-mca/Views/BottleneckAnalysis.cpp
The file was modifiedllvm/test/tools/llvm-mca/X86/SkylakeClient/bottleneck-analysis.s
Commit 3ecab8e4555aee0b4aa10c413696a67f55948c39 by Matthew.Arsenault
Reapply r372285 "GlobalISel: Don't materialize immarg arguments to
intrinsics"
This reverts r372314, reapplying r372285 and the commits which depend on
it (r372286-r372293, and r372296-r372297)
This was missing one switch to getTargetConstant in an untested case.
llvm-svn: 372338
The file was modifiedllvm/lib/Target/Mips/MipsInstrInfo.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
The file was modifiedllvm/lib/Target/X86/X86InstrTSX.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
The file was modifiedllvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZPatterns.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
The file was modifiedllvm/lib/Target/Mips/MipsMSAInstrInfo.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelLowering.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepOperands.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZOperators.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.sleep.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
The file was modifiedllvm/lib/Target/AMDGPU/VOP1Instructions.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZOperands.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrAltivec.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrVector.td
The file was modifiedllvm/lib/Target/X86/X86InstrAVX512.td
The file was modifiedllvm/lib/Target/Mips/Mips64InstrInfo.td
The file was addedllvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/lib/Target/ARM/ARMInstrInfo.td
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/BUFInstructions.td
The file was modifiedllvm/lib/Target/X86/X86InstrXOP.td
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoA.td
The file was modifiedllvm/lib/Target/X86/X86InstrSSE.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrBulkMemory.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
The file was modifiedllvm/lib/Target/Mips/MipsSEISelLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonIntrinsics.td
The file was modifiedllvm/lib/CodeGen/ScheduleDAGInstrs.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrVSX.td
The file was modifiedllvm/lib/Target/AMDGPU/DSInstructions.td
The file was modifiedllvm/lib/Target/Mips/MipsDSPInstrInfo.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
The file was modifiedllvm/lib/Target/X86/X86InstrMMX.td
The file was addedllvm/test/TableGen/immarg.td
The file was modifiedllvm/include/llvm/Target/TargetSelectionDAG.td
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrSystem.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td
The file was modifiedllvm/lib/Target/AMDGPU/SOPInstructions.td
The file was modifiedllvm/lib/Target/ARM/ARMInstrThumb2.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrFormats.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td
Commit 13e71ce69319d7acdd0e8d57b31c09545d9f2a45 by spatel
[Float2Int] avoid crashing on unreachable code (PR38502)
In the example from: https://bugs.llvm.org/show_bug.cgi?id=38502
...we hit infinite looping/crashing because we have non-standard IR - an
instruction operand is used before defined. This and other unusual
constructs are allowed in unreachable blocks, so avoid the problem by
using DominatorTree to step around landmines.
Differential Revision: https://reviews.llvm.org/D67766
llvm-svn: 372339
The file was modifiedllvm/test/Transforms/Float2Int/basic.ll
The file was modifiedllvm/lib/Transforms/Scalar/Float2Int.cpp
The file was modifiedllvm/test/Other/opt-Os-pipeline.ll
The file was modifiedllvm/test/Other/opt-O3-pipeline.ll
The file was modifiedllvm/test/Other/opt-O2-pipeline.ll
The file was modifiedllvm/include/llvm/Transforms/Scalar/Float2Int.h
Commit e2f9bc3b11baebbdd91ba0ae2faf30d39071ca54 by Alexander.Timofeev
[AMDGPU] Unnecessary -amdgpu-scalarize-global-loads=false flag removed
from min/max lit tests.
Reviewers: arsenm
Differential Revision: https://reviews.llvm.org/D67712
llvm-svn: 372340
The file was modifiedllvm/test/CodeGen/AMDGPU/sminmax.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/max.ll
Commit 7a67ed579520993fcd5ee9442db536ae4100bc23 by lebedev.ri
[InstCombine] Simplify @llvm.usub.with.overflow+non-zero check (PR43251)
Summary: This is again motivated by D67122 sanitizer check enhancement.
That patch seemingly worsens `-fsanitize=pointer-overflow` overhead from
25% to 50%, which strongly implies missing folds.
In this particular case, given
``` char* test(char& base, unsigned long offset) {
return &base - offset;
}
``` it will end up producing something like https://godbolt.org/z/luGEju
which after optimizations reduces down to roughly
``` declare void @use64(i64) define i1 @test(i8* dereferenceable(1)
%base, i64 %offset) {
%base_int = ptrtoint i8* %base to i64
%adjusted = sub i64 %base_int, %offset
call void @use64(i64 %adjusted)
%not_null = icmp ne i64 %adjusted, 0
%no_underflow = icmp ule i64 %adjusted, %base_int
%no_underflow_and_not_null = and i1 %not_null, %no_underflow
ret i1 %no_underflow_and_not_null
}
``` Without D67122 there was no `%not_null`, and in this particular case
we can "get rid of it", by merging two checks: Here we are checking:
`Base u>= Offset && (Base u- Offset) != 0`, but that is simply `Base u>
Offset`
Alive proofs: https://rise4fun.com/Alive/QOs
The `@llvm.usub.with.overflow` pattern itself is not handled here
because this is the main pattern, that we currently consider canonical.
https://bugs.llvm.org/show_bug.cgi?id=43251
Reviewers: spatel, nikic, xbolva00, majnemer
Reviewed By: xbolva00, majnemer
Subscribers: vsk, majnemer, xbolva00, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67356
llvm-svn: 372341
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
The file was modifiedllvm/test/Transforms/InstCombine/result-of-usub-is-non-zero-and-no-overflow.ll
Commit cb032aa2c773469ce6d1702ef2ec9b50e9e13b46 by francesco.petrogalli
[SVFS] Vector Function ABI demangling.
This patch implements the demangling functionality as described in the
Vector Function ABI. This patch will be used to implement the
SearchVectorFunctionSystem (SVFS) as described in the RFC:
http://lists.llvm.org/pipermail/llvm-dev/2019-June/133484.html
A fuzzer is added to test the demangling utility.
Patch by Sumedh Arani <sumedh.arani@arm.com>
Differential revision: https://reviews.llvm.org/D66024
llvm-svn: 372343
The file was modifiedllvm/lib/Analysis/CMakeLists.txt
The file was addedllvm/unittests/Analysis/VectorFunctionABITest.cpp
The file was modifiedllvm/unittests/Analysis/CMakeLists.txt
The file was modifiedllvm/include/llvm/Analysis/VectorUtils.h
The file was addedllvm/tools/vfabi-demangle-fuzzer/vfabi-demangler-fuzzer.cpp
The file was addedllvm/lib/Analysis/VFABIDemangling.cpp
The file was addedllvm/tools/vfabi-demangle-fuzzer/CMakeLists.txt
Commit aa6ef2eeacc9ea7069bc1194757478ca59e4e20e by llvmgnsyncbot
gn build: Merge r372343
llvm-svn: 372344
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/Analysis/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Analysis/BUILD.gn
Commit ca4c5deae5df418149c09b1843b43e06386c2d6a by Jinsong Ji
[NFC][PowerPC] Fast-isel VSX support test
We have fixed most of the VSX limitation in Fast-isel, so we can remove
the -mattr=-vsx for most testcases now.
llvm-svn: 372345
The file was modifiedllvm/test/CodeGen/PowerPC/fast-isel-ret.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fast-isel-call.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fast-isel-const.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fast-isel-load-store.ll
Commit d89f2d872df3e2426e0d54dc724a0e13bd94a577 by smeenai
[Analysis] Allow -scalar-evolution-max-iterations more than once
At present, `-scalar-evolution-max-iterations` is a `cl::Optional`
option, which means it demands to be passed exactly zero or one times.
Our build system makes it pretty tricky to guarantee this. We often
accidentally pass the flag more than once (but always with the same
value) which results in an error, after which compilation fails:
``` clang (LLVM option parsing): for the
-scalar-evolution-max-iterations option: may only occur zero or one
times!
```
It seems reasonable to allow -scalar-evolution-max-iterations to be
passed more than once. Quoting the [[
http://llvm.org/docs/CommandLine.html#controlling-the-number-of-occurrences-required-and-allowed
| documentation ]]:
> The cl::ZeroOrMore modifier ... indicates that your program will allow
the option to be specified zero or more times.
> ...
> If an option is specified multiple times for an option of the cl::opt
class, only the last value will be retained.
Original patch by: Enrico Bern Hardy Tanuwidjaja <etanuwid@fb.com>
Differential Revision: https://reviews.llvm.org/D67512
llvm-svn: 372346
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
The file was addedllvm/test/Analysis/ScalarEvolution/multiple-max-iterations.ll
Commit e6b2164723b06417dfe44d4bedcb3c2fd8a79c0d by kubakuderski
Don't use invalidated iterators in FlattenCFGPass
Summary: FlattenCFG may erase unnecessary blocks, which also invalidates
iterators to those erased blocks. Before this patch,
`iterativelyFlattenCFG` could try to increment a BB iterator after that
BB has been removed and crash.
This patch makes FlattenCFGPass use `WeakVH` to skip over erased blocks.
Reviewers: dblaikie, tstellar, davide, sanjoy, asbirlea, grosser
Reviewed By: asbirlea
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67672
llvm-svn: 372347
The file was modifiedllvm/lib/Transforms/Scalar/FlattenCFGPass.cpp
The file was modifiedllvm/test/Transforms/Util/flattencfg.ll
Commit f1b6bd403d52f41d0c55733387cf5f71753f3c25 by eugeni.stepanov
[lsan] Fix deadlock in dl_iterate_phdr.
Summary: Do not grab the allocator lock before calling dl_iterate_phdr.
This may cause a lock order inversion with (valid) user code that uses
malloc inside a dl_iterate_phdr callback.
Reviewers: vitalybuka, hctim
Subscribers: jfb, #sanitizers, llvm-commits
Tags: #sanitizers, #llvm
Differential Revision: https://reviews.llvm.org/D67738
llvm-svn: 372348
The file was modifiedcompiler-rt/lib/lsan/lsan_common.h
The file was modifiedcompiler-rt/lib/lsan/lsan_common_linux.cpp
The file was addedcompiler-rt/test/lsan/TestCases/Linux/libdl_deadlock.cpp
The file was modifiedcompiler-rt/lib/lsan/lsan_common.cpp
The file was modifiedcompiler-rt/lib/lsan/lsan_common_mac.cpp
Commit 1796aad50ca5de2447fdee5f22ce6f6a6379197f by dblaikie
llvm-reduce: Follow-up to 372280, now with more-better msan fixing
llvm-svn: 372349
The file was modifiedllvm/tools/llvm-reduce/deltas/ReduceBasicBlocks.cpp
Commit d487d6401d98ba7a759cd069b61ae67b286a3014 by Stanislav.Mekhanoshin
[AMDGPU] fixed underflow in getOccupancyWithNumVGPRs
The function could return zero if an extreme number or registers were
used. Minimal possible occupancy is 1.
Differential Revision: https://reviews.llvm.org/D67771
llvm-svn: 372350
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
Commit f5fcf6156656421c50b78aff1192b4a40603b86f by mitchphillips
Don't false-positive match against binary path.
copy-rel-abs.s uses llvm-objdump to generate output that's then run
through FileCheck. llvm-objdump prints the file path at the top of the
file, which means that any build path that contains 'zed' will get
false-matched. Ensure that 'zed' is only matched after the 'SYMBOL
TABLE:' output, preventing this from failing if your build directory is
~/build/sanitized-xxx/, or similar.
llvm-svn: 372351
The file was modifiedlld/test/ELF/copy-rel-abs.s
Commit 75fbb171c3093cb325972b989f240383711635f4 by Akira
[ObjC][ARC] Skip debug instructions when computing the insert point of
objc_release calls
This fixes a bug where the presence of debug instructions would cause
ARC optimizer to change the order of retain and release calls.
rdar://problem/55319419
llvm-svn: 372352
The file was modifiedllvm/lib/Transforms/ObjCARC/PtrState.cpp
The file was addedllvm/test/Transforms/ObjCARC/code-motion.ll
Commit 08f938bd1ae356544923042423ea3f30cd730bf8 by mitchphillips
Revert "[CUDA][HIP] Fix typo in `BestViableFunction`"
Broke the msan buildbots (see comments on rL372318 for more details).
This reverts commit eb231d15825ac345b546f4c99372d1cac8f14f02.
llvm-svn: 372353
The file was modifiedclang/test/SemaCUDA/function-overload.cu
The file was modifiedclang/test/SemaCUDA/implicit-member-target-collision-cxx11.cu
The file was modifiedclang/lib/Sema/SemaOverload.cpp
Commit b8fc6a91164a29c79dc179eab82a2f41fb4b4ac4 by michael.hliao
[CUDA][HIP] Re-apply part of r372318.
- r372318 causes violation of `use-of-uninitialized-value` detected by
MemorySanitizer. Once `Viable` field is set to false, `FailureKind`
needs setting as well as it will be checked during destruction if
`Viable` is not true.
- Revert the part trying to skip `std::vector` erasing.
llvm-svn: 372356
The file was modifiedclang/test/SemaCUDA/implicit-member-target-collision-cxx11.cu
The file was modifiedclang/test/SemaCUDA/function-overload.cu
The file was modifiedclang/lib/Sema/SemaOverload.cpp
Commit a4da991e4a4e7aef48c37293b20d74cd58dfc0f4 by e.menezes
[AArch64] Fix formatting (NFC)
llvm-svn: 372357
The file was modifiedllvm/lib/Target/AArch64/AArch64.td
Commit 0c3d4cfbadef74e7019ac6fc950a0c7034db79bf by tlively
[WebAssembly][NFC] Remove unnecessary braces
llvm-svn: 372358
The file was modifiedlld/wasm/Writer.cpp
Commit 40c3d6e33590054f095b5adfcd62ddc3c5c58e69 by richard-llvm
Model converted constant expressions as full-expressions.
This is groundwork for C++20's P0784R7, where non-trivial destructors
can be constexpr, so we need ExprWithCleanups markers in constant
expressions.
No functionality change intended.
llvm-svn: 372359
The file was modifiedclang/lib/Parse/ParseDecl.cpp
The file was modifiedclang/lib/Sema/SemaTemplate.cpp
The file was modifiedclang/lib/Sema/SemaOverload.cpp
The file was modifiedclang/lib/Sema/SemaStmt.cpp
Commit ccf8d5b8292afd91e811c6657d73682da66f46f5 by Alex Lorenz
Fix for stringized function-macro args continued across lines
In case of certain #define'd macros, there's a space just before line
continuation that the minimized-source lexer was missing to include,
resulting in invalid stringize.
Patch by: kousikk (Kousik Kumar)
Differential Revision: https://reviews.llvm.org/D67635
llvm-svn: 372360
The file was modifiedclang/lib/Lex/DependencyDirectivesSourceMinimizer.cpp
The file was modifiedclang/unittests/Lex/DependencyDirectivesSourceMinimizerTest.cpp
Commit 9dd57df26abfd2b7252fd4ce02d48f225930214e by comexk
[Consumed] Treat by-value class arguments as consuming by default, like
rvalue refs.
Differential Revision: https://reviews.llvm.org/D67743
llvm-svn: 372361
The file was modifiedclang/test/SemaCXX/warn-consumed-analysis.cpp
The file was modifiedclang/lib/Analysis/Consumed.cpp
Commit dd74f4839b1291810f376e0a5739ddd0abff91be by Matthew.Arsenault
MachineScheduler: Fix missing dependency with multiple subreg defs
If an instruction had multiple subregister defs, and one of them was
undef, this would improperly conclude all other lanes are killed. There
could still be other defs of those read-undef lanes in other operands.
This would improperly remove register uses from CurrentVRegUses, so the
visitation of later operands would not find the necessary register
dependency. This would also mean this would fail or not depending on how
different subregister def operands were ordered.
On an undef subregister def, scan the instruction for other subregister
defs and avoid killing those.
This possibly should be deferring removing anything from CurrentVRegUses
until the entire instruction has been processed instead.
llvm-svn: 372362
The file was addedllvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
The file was modifiedllvm/lib/CodeGen/ScheduleDAGInstrs.cpp
Commit 466fb68fce10d34963c2fd651de32bd3a4ddcd1f by apl
[NFCI] Always initialize const members of AttributeCommonInfo
Some compilers require that const fields of an object must be explicitly
initialized by the constructor. I ran into this issue building with
clang 3.8 on Ubuntu 16.04.
llvm-svn: 372363
The file was modifiedclang/include/clang/Basic/AttributeCommonInfo.h
Commit 627868ab7c3d42313634b0305ce498645f6c851c by hhb
Revert "Fix swig python package path"
Summary: This reverts commit 5a115e81cdd40c758b10c382aeffc0c8de6930e2.
Reviewers: JDevlieghere, ZeGentzy
Subscribers: mgorny, lldb-commits
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D67781
llvm-svn: 372364
The file was modifiedlldb/scripts/CMakeLists.txt
Commit 081cb7ef2370b42e4eeac086f472eec123174452 by craig.topper
[X86] Remove the special isBuildVectorOfConstantSDNodes handling from
LowerBUILD_VECTORvXi1.
The later code that generates a constant when there are some non-const
elements works basically the same and doesn't require there to be any
non-const elements.
llvm-svn: 372365
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 52621307bcab2013e8833f3317cebd63a6db3885 by saugustine
Use getTargetConstant for BLENDI, and add a test to catch it.
Summary: This fixes a crasher introduced by r372338.
Reviewers: echristo, arsenm
Subscribers: jvesely, wdng, nhaehnle, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67785
Tighten up the test case.
llvm-svn: 372366
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/isel-blendi-gettargetconstant.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 8c77674e0f4b8a1d64740088eaa0776197b9e350 by nicolasweber
llvm-undname: Delete an empty, unused method.
llvm-svn: 372367
The file was modifiedllvm/include/llvm/Demangle/MicrosoftDemangleNodes.h
The file was modifiedllvm/lib/Demangle/MicrosoftDemangleNodes.cpp
Commit 4aef105b43076e18e2d272a77491adc9533f5f3f by richard-llvm
Finish building the full-expression for a static_assert expression
before evaluating it rather than afterwards.
This is groundwork for C++20's P0784R7, where non-trivial destructors
can be constexpr, so we need ExprWithCleanups markers in constant
expressions.
No significant functionality change intended (though this fixes a bug
only visible through libclang / -ast-dump / tooling: we now store the
converted condition on the StaticAssertDecl rather than the original).
llvm-svn: 372368
The file was modifiedclang/test/Index/Core/index-source.cpp
The file was modifiedclang/lib/Sema/SemaDeclCXX.cpp
Commit a5db9ee71f81310f89204cde1dfb54fea9bd92f1 by maskray
[Object] Uncapitalize an error message
Test case will be added by my next commit.
llvm-svn: 372369
The file was modifiedllvm/lib/Object/Archive.cpp
Commit c768ad94b7f0be9feb86dd5cfcdb4158a5a28dd7 by maskray
[llvm-ar] Removes repetition in the error message
As per bug 40244, fixed an error where the error message was repeated.
Differential Revision: https://reviews.llvm.org/D67038 Patch by Yu Jian
(wyjw)
llvm-svn: 372370
The file was addedllvm/test/tools/llvm-ar/invalid-object-file.test
The file was modifiedllvm/tools/llvm-ar/llvm-ar.cpp
Commit a34f13f2bab3bb3a25ce999defb616558cbc3f4f by craig.topper
[X86] Use timm in MMX pinsrw/pextrw isel patterns. Add missing test
cases.
This fixes an isel failure after r372338.
llvm-svn: 372371
The file was modifiedllvm/test/CodeGen/X86/mmx-intrinsics.ll
The file was modifiedllvm/lib/Target/X86/X86InstrMMX.td
Commit e03663fbb8469e54e18666efcc3c0b691cc8fb1f by Yuanfang Chen
[llvm-readobj] flush output before crash
Otherwise the output could be lost.
llvm-svn: 372372
The file was modifiedllvm/tools/llvm-readobj/ARMWinEHPrinter.cpp
Commit 621c93ec1fd804f736cbcb58282ef037fa1a9c48 by craig.topper
[X86] Convert tbm_bextri_u32/tbm_bextri_u64 intrinsics TargetConstant
argument to a regular Constant during lowering.
We reuse an ISD opcode here that can be reached from BMI that doesn't
require it to be an immediate. Our isel patterns to match the TBM
immediate form require a Constant and not a TargetConstant.
We were accidentally getting the Constant due to a quirk of combineBEXTR
calling SimplifyDemandedBits. The call to SimplifyDemandedBits ended up
constant folding the TargetConstant to a regular Constant. But we should
probably instead be asserting if SimplifyDemandedBits on a
TargetConstant so we shouldn't rely on this behavior.
llvm-svn: 372373
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86IntrinsicsInfo.h
Commit 25040f8dec2e2dda5b0951744f9a32fb7aab3755 by gbreynoo
Reapply [llvm-ar] Include a line number when failing to parse an MRI
script
Reapply r372309
Errors that occur when reading an MRI script now include a corresponding
line number.
Differential Revision: https://reviews.llvm.org/D67449
llvm-svn: 372374
The file was modifiedllvm/test/Object/mri2.test
The file was modifiedllvm/test/Object/mri3.test
The file was modifiedllvm/test/Object/mri4.test
The file was modifiedllvm/tools/llvm-ar/llvm-ar.cpp
The file was modifiedllvm/test/tools/llvm-ar/mri-addlib.test
The file was addedllvm/test/tools/llvm-ar/mri-errors.test
Commit 8f21b5354729e2eead64411ece91e455cc527d7f by flo
[CallSiteSplitting] Remove unused includes (NFC).
llvm-svn: 372375
The file was modifiedllvm/include/llvm/Transforms/Scalar/CallSiteSplitting.h
Commit 15e27b0b6d9d51362fad85dbe95ac5b3fadf0a06 by jmolloy
[MachinePipeliner] Improve the TargetInstrInfo API
analyzeLoop/reduceLoopCount
The way MachinePipeliner uses these target hooks is stateful - we reduce
trip count by one per call to reduceLoopCount. It's a little overfit for
hardware loops, where we don't have to worry about stitching a loop
induction variable across prologs and epilogs (the induction variable is
implicit).
This patch introduces a new API:
  /// Analyze loop L, which must be a single-basic-block loop, and if
the
/// conditions can be understood enough produce a PipelinerLoopInfo
object.
virtual std::unique_ptr<PipelinerLoopInfo>
analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const;
The return value is expected to be an implementation of the abstract
class:
  /// Object returned by analyzeLoopForPipelining. Allows software
pipelining
/// implementations to query attributes of the loop being pipelined.
class PipelinerLoopInfo {
public:
   virtual ~PipelinerLoopInfo();
   /// Return true if the given instruction should not be pipelined and
should
   /// be ignored. An example could be a loop comparison, or induction
variable
   /// update with no users being pipelined.
   virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const
= 0;
    /// Create a condition to determine if the trip count of the loop is
greater
   /// than TC.
   ///
   /// If the trip count is statically known to be greater than TC,
return
   /// true. If the trip count is statically known to be not greater
than TC,
   /// return false. Otherwise return nullopt and fill out Cond with the
test
   /// condition.
   virtual Optional<bool>
   createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB,
                                SmallVectorImpl<MachineOperand> &Cond) =
0;
    /// Modify the loop such that the trip count is
   /// OriginalTC + TripCountAdjust.
   virtual void adjustTripCount(int TripCountAdjust) = 0;
    /// Called when the loop's preheader has been modified to
NewPreheader.
   virtual void setPreheader(MachineBasicBlock *NewPreheader) = 0;
    /// Called when the loop is being removed.
   virtual void disposed() = 0;
};
The Pipeliner (ModuloSchedule.cpp) can use this object to modify the
loop while allowing the target to hold its own state across all calls.
This API, in particular the disjunction of creating a trip count check
condition and adjusting the loop, improves the code quality in
ModuloSchedule.cpp.
llvm-svn: 372376
The file was modifiedllvm/include/llvm/CodeGen/ModuloSchedule.h
The file was modifiedllvm/lib/CodeGen/TargetInstrInfo.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetInstrInfo.h
The file was modifiedllvm/lib/CodeGen/ModuloSchedule.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonInstrInfo.h
The file was modifiedllvm/test/CodeGen/Hexagon/swp-epilog-phi7.ll
The file was modifiedllvm/lib/CodeGen/MachinePipeliner.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.h
Commit 4d69967f44116b4ad4b2810633045ffed119f7c3 by grimar
[yaml2obj/obj2yaml] - Do not trigger llvm_unreachable when
dumping/parsing relocations and e_machine is unsupported.
Currently when e_machine is set to something that is not supported by
YAML lib, then tools fail with llvm_unreachable.
In this patch I allow them to handle relocations in this case. It can be
used to dump and create objects for broken or unsupported targets.
Differential revision: https://reviews.llvm.org/D67657
llvm-svn: 372377
The file was addedllvm/test/tools/obj2yaml/relocation-unsupported-machine.yaml
The file was addedllvm/test/tools/yaml2obj/relocation-unsupported-machine.yaml
The file was modifiedllvm/lib/ObjectYAML/ELFYAML.cpp
Commit 9120829063de1885b88a1e274e17026552bbab68 by djordje.todorovic
[llvm-dwarfdump] Adjust Windows path to be acceptable by JSON
Backslash is a special character according to JSON specification, so we
should avoid that when printing a file path with the
--statistics option.
Differential Revision: https://reviews.llvm.org/D67699
llvm-svn: 372378
The file was modifiedllvm/tools/llvm-dwarfdump/Statistics.cpp
Commit 0ecf34dde3904079dc0f7b0569494c7118d9f08d by david.tellenbach
[NFC] Test commit, deleting some whitespace
llvm-svn: 372379
The file was modifiedllvm/docs/Atomics.rst
Commit 22a8f35ce0ed2b47934df458966a90509fd7f25a by kerry.mclaughlin
[IntrinsicEmitter] Add overloaded types for SVE intrinsics (Subdivide2 &
Subdivide4)
Summary: Both match the type of another intrinsic parameter of a vector
type, but where each element is subdivided to form a vector with more
elements of a smaller type.
Subdivide2Argument allows intrinsics such as the following to be
defined:
- declare <vscale x 4 x i32> @llvm.something.nxv4i32(<vscale x 8 x i16>)
Subdivide4Argument allows intrinsics such as:
- declare <vscale x 4 x i32> @llvm.something.nxv4i32(<vscale x 16 x i8>)
Tests are included in follow up patches which add intrinsics using these
types.
Reviewers: sdesmalen, SjoerdMeijer, greened, rovka
Reviewed By: sdesmalen
Subscribers: rovka, tschuett, jdoerfert, cfe-commits, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67549
llvm-svn: 372380
The file was modifiedllvm/include/llvm/IR/Intrinsics.h
The file was modifiedllvm/include/llvm/IR/Intrinsics.td
The file was modifiedllvm/include/llvm/IR/DerivedTypes.h
The file was modifiedllvm/utils/TableGen/IntrinsicEmitter.cpp
The file was modifiedllvm/lib/IR/Function.cpp
Commit 7335197147924b15163ded2177ddc3b7ae118712 by Raphael Isemann
[lldb][NFC] Remove unused include in TestLineEntry.cpp
llvm-svn: 372381
The file was modifiedlldb/unittests/Symbol/TestLineEntry.cpp
Commit 03475adcf720cdecf50cae7ef17c9b70883115df by nicolasweber
Revert r372366 "Use getTargetConstant for BLENDI, and add a test to
catch it."
This reverts commit 52621307bcab2013e8833f3317cebd63a6db3885.
Tests have been failing all night with
    [0/2] ACTION
//llvm/test:check-llvm(//llvm/utils/gn/build/toolchain:unix)
   -- Testing: 33647 tests, 64 threads --
   Testing: 0 .. 10..
   UNRESOLVED: LLVM ::
CodeGen/AMDGPU/GlobalISel/isel-blendi-gettargetconstant.ll (6943 of
33647)
   ******************** TEST 'LLVM ::
CodeGen/AMDGPU/GlobalISel/isel-blendi-gettargetconstant.ll' FAILED
********************
   Test has no run line!
   ********************
Since there were other concerns on https://reviews.llvm.org/D67785, I'm
just reverting for now.
llvm-svn: 372383
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was removedllvm/test/CodeGen/AMDGPU/GlobalISel/isel-blendi-gettargetconstant.ll
Commit 169cb63478aa047451786d8ccf6af4b721e3b271 by bjorn.a.pettersson
[AMDGPU] Use std::make_tuple to make some toolchains happy again
My toolchain stopped working (LLVM 8.0 , libstdc++ 5.4.0) after r372338.
The same problem was seen in clang-cuda-build buildbots:
clang-cuda-build/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:763:12:
error: chosen constructor is explicit in copy-initialization
   return {Reg, 0, nullptr};
          ^~~~~~~~~~~~~~~~~
/usr/bin/../lib/gcc/x86_64-linux-gnu/5.4.0/../../../../include/c++/5.4.0/tuple:479:19:
note: explicit constructor declared here
       constexpr tuple(_UElements&&... __elements)
                 ^
This commit adds explicit calls to std::make_tuple to work around the
problem.
llvm-svn: 372384
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Summary

  1. The LLD buildbot has some tests that are not reliable. Hopefully (details)
Commit 447a47d472e9ad0a529c0920a0db6231506d3e91 by gkistanova
The LLD buildbot has some tests that are not reliable. Hopefully
reducing the number of threads for the test will fix the issue. It seems
that the quotes around the parameters means it tries to take everything
as one argument. Bu using -j we can actually pass everything as one
argument by attaching the j to the sv.
Patch by Stefan Pintilie.
llvm-svn: 372342
The file was modifiedbuildbot/osuosl/master/config/builders.py