SuccessChanges

Summary

  1. BranchFolding - IsBetterFallthrough - assert non-null pointers. NFCI. (details)
  2. SemaStmt - silence static analyzer getAs<> null dereference warnings. (details)
  3. Remove redundant !HasDependentValue check. NFCI. (details)
  4. TreeTransform - silence static analyzer getAs<> null dereference (details)
  5. SemaTemplate - silence static analyzer getAs<> null dereference (details)
  6. [Diagnostics] Highlight expr's source range for -Wbool-operation (details)
  7. RewriteObjC - silence static analyzer getAs<> null dereference warnings. (details)
  8. [SelectionDAG] Add tests for LKK algorithm (details)
  9. Try to fix sphinx indentation error (details)
  10. [X86] lowerShuffleAsLanePermuteAndRepeatedMask - variable renames. NFCI. (details)
  11. [SLP] avoid reduction transform on patterns that the backend can (details)
  12. [X86][AVX] Push sign extensions of comparison bool results through (details)
  13. [FastISel] Copy the inline assembly dialect to the INLINEASM (details)
  14. AMDGPU/GlobalISel: Fix RegBankSelect for sendmsg intrinsics (details)
  15. GlobalISel: Partially implement lower for G_EXTRACT (details)
  16. AMDGPU/GlobalISel: Lower G_ATOMIC_CMPXCHG_WITH_SUCCESS (details)
  17. AMDGPU/GlobalISel: RegBankSelect DS GWS intrinsics (details)
  18. AMDGPU/GlobalISel: RegBankSelect mul24 intrinsics (details)
  19. AMDGPU/GlobalISel: Fall back on weird G_EXTRACT offsets (details)
  20. [clang-format][docs] Fix the Google C++ and Chromium style guide URLs (details)
  21. [X86] Enable AVX512BW for memcmp() (details)
Commit f609c0a303e4e20356d565d2bd4ecec76ed7ca7e by llvm-dev
BranchFolding - IsBetterFallthrough - assert non-null pointers. NFCI.
Silences static analyzer null dereference warnings.
llvm-svn: 373823
The file was modifiedllvm/lib/CodeGen/BranchFolding.cpp
Commit 20692a0d3d3e837e6f81d477cbc07b4eb449d380 by llvm-dev
SemaStmt - silence static analyzer getAs<> null dereference warnings.
NFCI.
The static analyzer is warning about potential null dereferences, but we
should be able to use castAs<> directly and if not assert will fire for
us.
llvm-svn: 373824
The file was modifiedclang/lib/Sema/SemaStmt.cpp
Commit 0e82722f9a10f8ad3cde686bbd9726b08962a024 by llvm-dev
Remove redundant !HasDependentValue check. NFCI.
Fixes cppcheck warning.
llvm-svn: 373825
The file was modifiedclang/lib/Sema/SemaStmt.cpp
Commit 22b6873195618fbbe90e30a2921a2984ac95ed20 by llvm-dev
TreeTransform - silence static analyzer getAs<> null dereference
warnings. NFCI.
The static analyzer is warning about potential null dereferences, but we
should be able to use castAs<> directly and if not assert will fire for
us.
llvm-svn: 373826
The file was modifiedclang/lib/Sema/TreeTransform.h
Commit f4cc3b3e10edd5c8d9b23f1d6806829d20b2c9df by llvm-dev
SemaTemplate - silence static analyzer getAs<> null dereference
warnings. NFCI.
The static analyzer is warning about potential null dereferences, but we
should be able to use castAs<> directly and if not assert will fire for
us.
llvm-svn: 373827
The file was modifiedclang/lib/Sema/SemaTemplate.cpp
Commit 83b81c1f6ee878ffe458aee3162ce0ef004d3374 by david.bolvansky
[Diagnostics] Highlight expr's source range for -Wbool-operation
Warning message looks better; and GCC adds it too.
llvm-svn: 373828
The file was modifiedclang/lib/Sema/SemaExpr.cpp
Commit 43bbca922844617610a4921bb646e49528059117 by llvm-dev
RewriteObjC - silence static analyzer getAs<> null dereference warnings.
NFCI.
The static analyzer is warning about potential null dereferences, but we
should be able to use castAs<> directly and if not assert will fire for
us.
llvm-svn: 373829
The file was modifiedclang/lib/Frontend/Rewrite/RewriteObjC.cpp
Commit 41c934acaf8539dedad4b48bbc88580c74fed25a by david.bolvansky
[SelectionDAG] Add tests for LKK algorithm
Added some tests testing urem and srem operations with a constant
divisor.
Patch by TG908 (Tim Gymnich)
Differential Revision: https://reviews.llvm.org/D68421
llvm-svn: 373830
The file was addedllvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
The file was addedllvm/test/CodeGen/RISCV/urem-lkk.ll
The file was addedllvm/test/CodeGen/X86/srem-vector-lkk.ll
The file was addedllvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
The file was addedllvm/test/CodeGen/X86/urem-lkk.ll
The file was addedllvm/test/CodeGen/AArch64/srem-vector-lkk.ll
The file was addedllvm/test/CodeGen/PowerPC/srem-lkk.ll
The file was addedllvm/test/CodeGen/RISCV/srem-lkk.ll
The file was addedllvm/test/CodeGen/RISCV/srem-vector-lkk.ll
The file was addedllvm/test/CodeGen/PowerPC/urem-lkk.ll
The file was addedllvm/test/CodeGen/AArch64/srem-lkk.ll
The file was addedllvm/test/CodeGen/AArch64/urem-lkk.ll
The file was addedllvm/test/CodeGen/AArch64/urem-vector-lkk.ll
The file was addedllvm/test/CodeGen/X86/urem-vector-lkk.ll
The file was addedllvm/test/CodeGen/X86/srem-lkk.ll
The file was addedllvm/test/CodeGen/RISCV/urem-vector-lkk.ll
Commit 68f21b360b91df88b87aebec5c5dbc5d68d42a6d by llvm-dev
Try to fix sphinx indentation error
llvm-svn: 373831
The file was modifiedclang/docs/ReleaseNotes.rst
Commit 9ecacb0d54fb89dc7e6da66d9ecae934ca5c01d4 by llvm-dev
[X86] lowerShuffleAsLanePermuteAndRepeatedMask - variable renames. NFCI.
Rename some variables to match lowerShuffleAsRepeatedMaskAndLanePermute
- prep work toward adding some equivalent sublane functionality.
llvm-svn: 373832
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit e2321bb4488a81b87742f3343e3bdf8e161aa35b by spatel
[SLP] avoid reduction transform on patterns that the backend can
load-combine
I don't see an ideal solution to these 2 related, potentially large,
perf regressions: https://bugs.llvm.org/show_bug.cgi?id=42708
https://bugs.llvm.org/show_bug.cgi?id=43146
We decided that load combining was unsuitable for IR because it could
obscure other optimizations in IR. So we removed the LoadCombiner pass
and deferred to the backend. Therefore, preventing SLP from destroying
load combine opportunities requires that it recognizes patterns that
could be combined later, but not do the optimization itself ( it's not a
vector combine anyway, so it's probably out-of-scope for SLP).
Here, we add a scalar cost model adjustment with a conservative pattern
match and cost summation for a multi-instruction sequence that can
probably be reduced later. This should prevent SLP from creating a
vector reduction unless that sequence is extremely cheap.
In the x86 tests shown (and discussed in more detail in the bug
reports), SDAG combining will produce a single instruction on these
tests like:
  movbe   rax, qword ptr [rdi]
or:
  mov     rax, qword ptr [rdi]
Not some (half) vector monstrosity as we currently do using SLP:
  vpmovzxbq       ymm0, dword ptr [rdi + 1] # ymm0 = mem[0],zero,zero,..
vpsllvq ymm0, ymm0, ymmword ptr [rip + .LCPI0_0]
movzx   eax, byte ptr [rdi]
movzx   ecx, byte ptr [rdi + 5]
shl     rcx, 40
movzx   edx, byte ptr [rdi + 6]
shl     rdx, 48
or      rdx, rcx
movzx   ecx, byte ptr [rdi + 7]
shl     rcx, 56
or      rcx, rdx
or      rcx, rax
vextracti128    xmm1, ymm0, 1
vpor    xmm0, xmm0, xmm1
vpshufd xmm1, xmm0, 78          # xmm1 = xmm0[2,3,0,1]
vpor    xmm0, xmm0, xmm1
vmovq   rax, xmm0
or      rax, rcx
vzeroupper
ret
Differential Revision: https://reviews.llvm.org/D67841
llvm-svn: 373833
The file was modifiedllvm/lib/Analysis/TargetTransformInfo.cpp
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfo.h
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/bad-reduction.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 8815be04ec1f333564591d9593735f22efa9bee5 by llvm-dev
[X86][AVX] Push sign extensions of comparison bool results through
bitops (PR42025)
As discussed on PR42025, with more complex boolean math we can end up
with many truncations/extensions of the comparison results through each
bitop.
This patch handles the cases introduced in combineBitcastvxi1 by pushing
the sign extension through the AND/OR/XOR ops so its just the original
SETCC ops that gets extended.
Differential Revision: https://reviews.llvm.org/D68226
llvm-svn: 373834
The file was modifiedllvm/test/CodeGen/X86/bitcast-and-setcc-256.ll
The file was modifiedllvm/test/CodeGen/X86/bitcast-and-setcc-512.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 2decdf42b95a8bdcbd33cd73e82a4efc76b91494 by craig.topper
[FastISel] Copy the inline assembly dialect to the INLINEASM
instruction.
Fixes PR43575.
llvm-svn: 373836
The file was addedllvm/test/CodeGen/X86/pr43575.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/FastISel.cpp
Commit 69c65a86097f11450a50af0c8213a0ee47983145 by Matthew.Arsenault
AMDGPU/GlobalISel: Fix RegBankSelect for sendmsg intrinsics
This wasn't updated for the immarg handling change.
llvm-svn: 373837
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit a5b9c756745ea88631277ab00c1b26f45f9d7e11 by Matthew.Arsenault
GlobalISel: Partially implement lower for G_EXTRACT
Turn into shift and truncate. Doesn't yet handle pointers.
llvm-svn: 373838
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
Commit bcd6b1d209048036593255b672b6b9ac27ee3511 by Matthew.Arsenault
AMDGPU/GlobalISel: Lower G_ATOMIC_CMPXCHG_WITH_SUCCESS
llvm-svn: 373839
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg-with-success.mir
Commit c0ec72d4f859fed86979ea63f708190cee3fc23e by Matthew.Arsenault
AMDGPU/GlobalISel: RegBankSelect DS GWS intrinsics
llvm-svn: 373840
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
Commit 786a3953baccc66f85e3a6c0053ce0f7d815de00 by Matthew.Arsenault
AMDGPU/GlobalISel: RegBankSelect mul24 intrinsics
llvm-svn: 373841
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit e59296a05191cd7cb23f9c444e8b173e479b49d7 by Matthew.Arsenault
AMDGPU/GlobalISel: Fall back on weird G_EXTRACT offsets
llvm-svn: 373842
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit c209598268b3c8923371c16c639c3d59dfd99690 by mydeveloperday
[clang-format][docs] Fix the Google C++ and Chromium style guide URLs
Summary: The Google C++ and Chromium style guides are broken in the
clang-format docs. This patch updates them.
Reviewers: djasper, MyDeveloperDay
Reviewed By: MyDeveloperDay
Subscribers: cfe-commits
Tags: #clang
Patch by: m4tx
Differential Revision: https://reviews.llvm.org/D61256
llvm-svn: 373844
The file was modifiedclang/docs/ClangFormatStyleOptions.rst
Commit 7653ff398d28851b211e81fa6ab22dd94de16f92 by dave
[X86] Enable AVX512BW for memcmp()
llvm-svn: 373845
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/setcc-wide-types.ll
The file was modifiedllvm/test/CodeGen/X86/memcmp.ll