SuccessChanges

Summary

  1. [RISCV] Define __riscv_cmodel_medlow and __riscv_cmodel_medany correctly (details)
  2. [bugpoint] Add support for -Oz and properly enable -Os. (details)
  3. [RISCV] Add option aliases: -mcmodel=medany and -mcmodel=medlow (details)
  4. [llvm-objcopy] - Remove python invocations from 2 test cases. (details)
  5. [Clang] Pragma vectorize_width() implies vectorize(enable) (details)
  6. [llvm-readobj] - Refactor the code. (details)
  7. [LoopUnroll] Use LoopSize+1 as threshold, to allow unrolling loops (details)
  8. [ARM] LE support in ConstantIslands (details)
  9. [AMDGPU]: PHI Elimination hooks added for custom COPY insertion. Fixed (details)
  10. [llvm-readobj] - Fix a TODO in elf-reloc-zero-name-or-value.test. (details)
  11. [llvm-ar] Parse 'h' and '-h': display help and exit (details)
  12. [llvm-readobj] - Fix BB after r372087. (details)
  13. [lldb] [Process/gdb-remote] Fix defaulting signal to invalid in action (details)
  14. [SimplifyLibCalls] Mark known arguments with nonnull (details)
  15. Patch from Phabricator (details)
  16. [NFC} Updated test (details)
  17. [ELF][AARCH64] Refactor AArchErrataFix to match changes in ARMErrataFix (details)
  18. [NFC] Updated test (details)
  19. [SimplifyLibCalls] Fix -Wunused-result after D53342/r372091 (details)
  20. [NFCI] Fixed buildbots (details)
  21. [InstCombine] Annotate strdup with deref_or_null (details)
  22. [SVE][MVT] Fixed-length vector MVT ranges (details)
Commit 645593844164187a2de37b40e62cd790cfb48a03 by kito.cheng
[RISCV] Define __riscv_cmodel_medlow and __riscv_cmodel_medany correctly
RISC-V LLVM was only implement small/medlow code model, so it defined
__riscv_cmodel_medlow directly without check.
Now, we have medium/medany code model in RISC-V back-end, it should
define according the actually code model.
Reviewed By: lewis-revill
Differential Revision: https://reviews.llvm.org/D67065
llvm-svn: 372078
The file was modifiedclang/lib/Basic/Targets/RISCV.cpp
The file was addedclang/test/Preprocessor/riscv-cmodel.c
Commit 5c17323dd8eeeb0d2d9c17c4ad0200c8a4e4ded7 by flo
[bugpoint] Add support for -Oz and properly enable -Os.
This patch adds -Oz as option and also properly enables support for -Os.
Currently, the existing check for -Os is dead, because the enclosing if
only checks of O1, O2 and O3.
There is still a difference between the -Oz pipeline compared to opt,
but I have not been able to track that down yet.
Reviewers: bogner, sebpop, efriedma
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D67593
llvm-svn: 372079
The file was modifiedllvm/tools/bugpoint/bugpoint.cpp
Commit 42fe2fc8c9359f300413cbd0f105ff0eb9559d6f by kito.cheng
[RISCV] Add option aliases: -mcmodel=medany and -mcmodel=medlow
RISC-V GCC use -mcmodel=medany and -mcmodel=medlow, but LLVM use
-mcmodel=small and -mcmodel=medium.
Add those two option aliases for provide same user interface between GCC
and LLVM.
Reviewed By: lenary
Differential Revision: https://reviews.llvm.org/D67066
llvm-svn: 372080
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/test/Preprocessor/riscv-cmodel.c
Commit a5dfa70806be78c5e07f14b14c758a4223935024 by grimar
[llvm-objcopy] - Remove python invocations from 2 test cases.
It is possible to use yaml2obj to create sections with overlapping
sh_offset now. This patch does that.
Differential revision: https://reviews.llvm.org/D67610
llvm-svn: 372081
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/overlapping-sections.test
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/overlapping-sections-in-segments.test
Commit e573a9c03566814e925bf083c6c3c785273f80ae by sjoerd.meijer
[Clang] Pragma vectorize_width() implies vectorize(enable)
Specifying the vectorization width was supposed to implicitly enable
vectorization, except that it wasn't really doing this. It was only
setting the vectorize.width metadata, but not vectorize.enable.
This should fix PR27643.
Differential Revision: https://reviews.llvm.org/D66290
llvm-svn: 372082
The file was modifiedclang/lib/CodeGen/CGLoopInfo.cpp
The file was modifiedclang/test/CodeGenCXX/pragma-loop.cpp
The file was modifiedclang/test/CodeGenCXX/pragma-loop-predicate.cpp
Commit 505553495c43b963512d7ae33a2aa9fe6769a15f by grimar
[llvm-readobj] - Refactor the code.
It's a straightforward refactoring that allows to simplify and
encapsulate the code.
Differential revision: https://reviews.llvm.org/D67624
llvm-svn: 372083
The file was modifiedllvm/include/llvm/Object/ELFObjectFile.h
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
Commit 1bd58870e5bd715c7bcbd1180bd50c4f4c7663ff by flo
[LoopUnroll] Use LoopSize+1 as threshold, to allow unrolling loops
matching LoopSize.
We use `< UP.Threshold` later on, so we should use LoopSize + 1, to
allow unrolling if the result won't exceed to loop size.
Fixes PR43305.
Reviewers: efriedma, dmgreen, paquette
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D67594
llvm-svn: 372084
The file was modifiedllvm/test/Transforms/LoopUnroll/AArch64/unroll-optsize.ll
The file was addedllvm/test/Transforms/LoopUnroll/optsize-loop-size.ll
The file was modifiedllvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
Commit 95b28a4c728adfebd30406d88151fb0df51a6c5b by sam.parker
[ARM] LE support in ConstantIslands
The low-overhead branch extension provides a loop-end 'LE' instruction
that performs no decrement nor compare, it just jumps backwards. This
patch modifies the constant islands pass to try to insert LE
instructions in place of a Thumb2 conditional branch, instead of
shrinking it. This only happens if a cmp can be converted to a cbn/z and
used to exit the loop.
Differential Revision: https://reviews.llvm.org/D67404
llvm-svn: 372085
The file was modifiedllvm/test/CodeGen/ARM/O3-pipeline.ll
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-reorder.mir
The file was modifiedllvm/lib/Target/ARM/ARMConstantIslandPass.cpp
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-le-simple.ll
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-cbnz.mir
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec.mir
Commit 6524a7a2b9ca072bd7f7b4355d1230e70c679d2f by Alexander.Timofeev
[AMDGPU]: PHI Elimination hooks added for custom COPY insertion. Fixed
Defferential Revision: https://reviews.llvm.org/D67101
Reviewers: rampitec, vpykhtin llvm-svn: 372086
The file was addedllvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.h
The file was modifiedllvm/include/llvm/CodeGen/TargetInstrInfo.h
The file was modifiedllvm/lib/CodeGen/PHIElimination.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/phi-elimination-assertion.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Commit de1bef0b1b2d111e07450686843dec76e2763130 by grimar
[llvm-readobj] - Fix a TODO in elf-reloc-zero-name-or-value.test.
The "TODO" mentioned was:
"Add test for symbol with no name but with a value once yaml2obj allows
referencing symbols with no name from relocations."
We can do it now.
Differential revision: https://reviews.llvm.org/D67609
llvm-svn: 372087
The file was modifiedllvm/test/tools/llvm-readobj/elf-reloc-zero-name-or-value.test
Commit 1ecba6f8efd2bdc466b4811081573186abd9a975 by maskray
[llvm-ar] Parse 'h' and '-h': display help and exit
Support `llvm-ar h` and `llvm-ar -h` because they may be what users try
at first. Note, operation 'h' is undocumented in GNU ar.
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D67560
llvm-svn: 372088
The file was modifiedllvm/tools/llvm-ar/llvm-ar.cpp
The file was addedllvm/test/tools/llvm-ar/help-message.test
Commit 48de660bbf0d824df77402c8856320fe534c2615 by grimar
[llvm-readobj] - Fix BB after r372087.
Seems I forgot to update the number of bytes checked.
llvm-svn: 372089
The file was modifiedllvm/test/tools/llvm-readobj/elf-reloc-zero-name-or-value.test
Commit e4d25e9e16278d7926ec43c6ea7571e869d0a619 by mgorny
[lldb] [Process/gdb-remote] Fix defaulting signal to invalid in action
list
Fix processing of "C" packet with signal for the whole process to
default signal value for action list to LLDB_INVALID_SIGNAL_NUMBER
rather than 0.
Differential Revision: https://reviews.llvm.org/D67625
llvm-svn: 372090
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
Commit e80fcf03407acd6429d07e4a45185ac546ffa37c by david.bolvansky
[SimplifyLibCalls] Mark known arguments with nonnull
Reviewers: efriedma, jdoerfert
Reviewed By: jdoerfert
Subscribers: ychen, rsmith, joerg, aaron.ballman, lebedev.ri, uenoku,
jdoerfert, hfinkel, javed.absar, spatel, dmgreen, llvm-commits
Differential Revision: https://reviews.llvm.org/D53342
llvm-svn: 372091
The file was modifiedllvm/test/Analysis/TypeBasedAliasAnalysis/memcpyopt.ll
The file was modifiedllvm/test/CodeGen/X86/no-plt-libcalls.ll
The file was modifiedllvm/test/Transforms/InstCombine/memset-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/mempcpy.ll
The file was modifiedllvm/test/Transforms/InstCombine/strncmp-2.ll
The file was modifiedllvm/test/Transforms/InstCombine/strncpy-2.ll
The file was modifiedllvm/test/Transforms/InstCombine/memcmp-constant-fold.ll
The file was modifiedllvm/test/Transforms/InstCombine/strncat-3.ll
The file was modifiedllvm/test/Transforms/InstCombine/objsize.ll
The file was modifiedllvm/test/Transforms/InstCombine/stpcpy_chk-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/memmove_chk-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/fortify-folding.ll
The file was modifiedllvm/test/Other/cgscc-libcall-update.ll
The file was modifiedllvm/test/Transforms/InstCombine/memcpy-from-global.ll
The file was modifiedllvm/test/Transforms/InstCombine/strncpy-1.ll
The file was modifiedllvm/test/Analysis/BasicAA/gep-alias.ll
The file was modifiedllvm/test/Transforms/InstCombine/strrchr-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/snprintf.ll
The file was modifiedllvm/test/Transforms/InstCombine/strcmp-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/mem-deref-bytes-addrspaces.ll
The file was modifiedllvm/test/Transforms/InstCombine/getelementptr.ll
The file was modifiedllvm/test/Transforms/InstCombine/mem-deref-bytes.ll
The file was modifiedllvm/test/Transforms/InstCombine/memcpy-to-load.ll
The file was addedllvm/test/Transforms/InstCombine/memrchr.ll
The file was modifiedllvm/test/Transforms/InstCombine/ARM/strcmp.ll
The file was modifiedllvm/test/Transforms/InstCombine/strcspn-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/strpbrk-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/malloc-free-delete.ll
The file was modifiedllvm/test/Transforms/InstCombine/strcmp-memcmp.ll
The file was modifiedllvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h
The file was modifiedllvm/test/Transforms/InstCombine/strncpy_chk-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/strstr-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/stpcpy-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/memcpy.ll
The file was modifiedllvm/test/Transforms/InstCombine/puts-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/printf-2.ll
The file was modifiedllvm/test/Transforms/InstCombine/memchr.ll
The file was modifiedllvm/test/Transforms/InstCombine/strchr-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/memset_chk-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/strcpy-1.ll
The file was modifiedllvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
The file was modifiedllvm/test/Transforms/InstCombine/sprintf-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/strcpy_chk-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/strncmp-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/printf-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/strlen-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/align-addr.ll
The file was modifiedllvm/test/Transforms/InstCombine/memcpy_chk-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/strncat-2.ll
Commit e38695a0255c9e7b53639f349f8101bae1ce5c04 by luismarques
Patch from Phabricator
llvm-svn: 372092
The file was modifiedllvm/test/CodeGen/RISCV/double-previous-failure.ll
The file was modifiedllvm/test/CodeGen/RISCV/imm-cse.ll
The file was modifiedllvm/test/CodeGen/RISCV/callee-saved-gprs.ll
The file was modifiedllvm/test/CodeGen/RISCV/add-before-shl.ll
The file was modifiedllvm/test/CodeGen/RISCV/remat.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-select-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/imm.ll
The file was modifiedllvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-imm.ll
The file was modifiedllvm/test/CodeGen/RISCV/fp128.ll
The file was modifiedllvm/test/CodeGen/RISCV/atomic-cmpxchg-flag.ll
The file was modifiedllvm/test/CodeGen/RISCV/mem.ll
The file was modifiedllvm/test/CodeGen/RISCV/select-optimize-multiple.ll
The file was modifiedllvm/test/CodeGen/RISCV/mem64.ll
The file was modifiedllvm/test/CodeGen/RISCV/alloca.ll
The file was modifiedllvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-br-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
The file was modifiedllvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll
The file was modifiedllvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
The file was modifiedllvm/test/CodeGen/RISCV/shifts.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/get-setcc-result-type.ll
The file was modifiedllvm/test/CodeGen/RISCV/indirectbr.ll
The file was modifiedllvm/test/CodeGen/RISCV/compress.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
The file was modifiedllvm/test/CodeGen/RISCV/blockaddress.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-select-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-arith.ll
The file was modifiedllvm/test/CodeGen/RISCV/setcc-logic.ll
The file was modifiedllvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64i-complex-float.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64f-float-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-imm.ll
The file was modifiedllvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-intrinsics.ll
The file was modifiedllvm/test/CodeGen/RISCV/div.ll
The file was modifiedllvm/test/CodeGen/RISCV/atomic-rmw.ll
The file was modifiedllvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
The file was modifiedllvm/test/CodeGen/RISCV/lsr-legaladdimm.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVSubtarget.h
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/codemodel-lowering.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
The file was modifiedllvm/test/CodeGen/RISCV/split-offsets.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-mem.ll
The file was modifiedllvm/test/CodeGen/RISCV/arith-with-overflow.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-br-fcmp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll
The file was modifiedllvm/test/CodeGen/RISCV/vararg.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-arith.ll
The file was modifiedllvm/test/CodeGen/RISCV/mul.ll
The file was modifiedllvm/test/CodeGen/RISCV/frame-info.ll
The file was modifiedllvm/test/CodeGen/RISCV/alu64.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/bare-select.ll
The file was modifiedllvm/test/CodeGen/RISCV/addcarry.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-mem.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-intrinsics.ll
The file was modifiedllvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-calling-conv.ll
The file was modifiedllvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
The file was modifiedllvm/test/CodeGen/RISCV/legalize-fneg.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-lp64.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-fcmp.ll
Commit 3d33e97be638bb8e91481decb1da07d8123ec17f by david.bolvansky
[NFC} Updated test
llvm-svn: 372093
The file was modifiedllvm/test/Transforms/CodeGenPrepare/X86/memset_chk-simplify-nobuiltin.ll
Commit 43d32cdd8717c3a6c35bd47d1e32789c854e6955 by peter.smith
[ELF][AARCH64] Refactor AArchErrataFix to match changes in ARMErrataFix
NFC.
D67284 introduced ARMErrataFix.cpp which was derived from
AArch64ErrataFix.cpp. There were some useful refactoring changes made to
ARMErrataFix.cpp made as part of the review. This change applies the
relevant changes back to AArch64ErrataFix.cpp.
Main changes are:
- Old style variable names in comments like IS, are now new style isec.
- Simplify init() collection of mappingSymbols to always start with a
code mapping symbol.
- Simplify logic in mergeCmp().
- Fix one 80 column overflow caused by IS -> isec transformation.
Differential Revision: https://reviews.llvm.org/D67622
llvm-svn: 372094
The file was modifiedlld/ELF/AArch64ErrataFix.cpp
Commit 957b9cdd2692178b9635cbbbcb94e78a5bc24473 by david.bolvansky
[NFC] Updated test
llvm-svn: 372095
The file was modifiedclang/test/CodeGen/tbaa-struct.cpp
Commit 83517637095060bc045a879caeecd2f2d8ea0e1f by maskray
[SimplifyLibCalls] Fix -Wunused-result after D53342/r372091
llvm-svn: 372096
The file was modifiedllvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
Commit 3a3dddd9d72edecc774efaee153e876fe74fed6c by david.bolvansky
[NFCI] Fixed buildbots
llvm-svn: 372097
The file was modifiedllvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
Commit be2487a2ba43f3929c894e8cf8fe3ddb0b9c6a24 by david.bolvansky
[InstCombine] Annotate strdup with deref_or_null
llvm-svn: 372098
The file was modifiedllvm/include/llvm/Analysis/MemoryBuiltins.h
The file was modifiedllvm/test/Transforms/InstCombine/deref-alloc-fns.ll
The file was modifiedllvm/lib/Analysis/MemoryBuiltins.cpp
The file was modifiedllvm/test/Transforms/InstCombine/objsize.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
Commit 1a9195d817d35a0464394018a3575ccfe49eda80 by graham.hunter
[SVE][MVT] Fixed-length vector MVT ranges
  * Reordered MVT simple types to group scalable vector types
   together.
* New range functions in MachineValueType.h to only iterate over
   the fixed-length int/fp vector types.
* Stopped backends which don't support scalable vector types from
   iterating over scalable types.
Reviewers: sdesmalen, greened
Reviewed By: greened
Differential Revision: https://reviews.llvm.org/D66339
llvm-svn: 372099
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelLowering.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/utils/TableGen/CodeGenDAGPatterns.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLowering.cpp
The file was modifiedllvm/lib/CodeGen/TargetLoweringBase.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/include/llvm/Support/MachineValueType.h
The file was modifiedllvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/Mips/MipsISelLowering.cpp
The file was modifiedllvm/lib/Target/Mips/MipsSEISelLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/ValueTypes.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonSubtarget.h
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
The file was modifiedllvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/Sparc/SparcISelLowering.cpp