FailedChanges

Summary

  1. Remove -DLLVM_USE_LINKER from Windows self host bots. LLVM_USE_LINKER sets the -fuse-ld. This is redundant as the linker is set to lld-link. Differential Revision: https://reviews.llvm.org/D69098
Revision 375212 by russell_gallop:
Remove -DLLVM_USE_LINKER from Windows self host bots.

LLVM_USE_LINKER sets the -fuse-ld. This is redundant as the linker is set to
lld-link.

Differential Revision: https://reviews.llvm.org/D69098
Change TypePath in RepositoryPath in Workspace
The file was modified/zorg/trunk/zorg/buildbot/builders/annotated/clang-windows.pyzorg/buildbot/builders/annotated/clang-windows.py
The file was modified/zorg/trunk/zorg/buildbot/builders/annotated/sanitizer-windows.pyzorg/buildbot/builders/annotated/sanitizer-windows.py

Summary

  1. [InstCombine] Pre-commit of test case showing miscompile bug in (details)
  2. [InstCombine] Fix miscompile bug in canEvaluateShuffled (details)
  3. [AArch64][SVE] Implement unpack intrinsics (details)
Commit 459134064daeef03a762979ab162587f94361cdc by bjorn.a.pettersson
[InstCombine] Pre-commit of test case showing miscompile bug in
canEvaluateShuffled
Adding the reproducer from  https://bugs.llvm.org/show_bug.cgi?id=43689,
showing that instcombine is doing a bad transform. It transforms
  %0 = insertelement <2 x i16> undef, i16 %a, i32 0
%1 = srem <2 x i16> %0, <i16 2, i16 1>
%2 = shufflevector <2 x i16> %1, <2 x i16> undef, <2 x i32> <i32 undef,
i32 0>
into
   %1 = insertelement <2 x i16> undef, i16 %a, i32 1
  %2 = srem <2 x i16> %1, <i16 undef, i16 2>
The undef denominator makes the whole srem undefined.
llvm-svn: 375207
The file was addedllvm/test/Transforms/InstCombine/shufflevector-div-rem.ll
Commit 6456252dbf67f26f88873e92c0813ebf8a1f96a3 by bjorn.a.pettersson
[InstCombine] Fix miscompile bug in canEvaluateShuffled
Summary: Add restrictions in canEvaluateShuffled to prevent that we for
example transform
  %0 = insertelement <2 x i16> undef, i16 %a, i32 0
%1 = srem <2 x i16> %0, <i16 2, i16 1>
%2 = shufflevector <2 x i16> %1, <2 x i16> undef, <2 x i32> <i32 undef,
i32 0>
into
   %1 = insertelement <2 x i16> undef, i16 %a, i32 1
  %2 = srem <2 x i16> %1, <i16 undef, i16 2>
as having an undef denominator makes the srem undefined (for all vector
elements).
Fixes: https://bugs.llvm.org/show_bug.cgi?id=43689
Reviewers: spatel, lebedev.ri
Reviewed By: spatel, lebedev.ri
Subscribers: lebedev.ri, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69038
llvm-svn: 375208
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
The file was modifiedllvm/test/Transforms/InstCombine/shufflevector-div-rem.ll
Commit 0c7cc383e5b846bc9e9fcc599d3f342333f5c963 by kerry.mclaughlin
[AArch64][SVE] Implement unpack intrinsics
Summary: Implements the following intrinsics:
- int_aarch64_sve_sunpkhi
- int_aarch64_sve_sunpklo
- int_aarch64_sve_uunpkhi
- int_aarch64_sve_uunpklo
This patch also adds AArch64ISD nodes for UNPK instead of implementing
the intrinsics directly, as they are required for a future patch which
implements the sign/zero extension of legal vectors.
This patch includes tests for the Subdivide2Argument type added by
D67549
Reviewers: sdesmalen, SjoerdMeijer, greened, rengolin, rovka
Reviewed By: greened
Subscribers: tschuett, kristof.beyls, rkruppe, psnobl, cfe-commits,
llvm-commits
Differential Revision: https://reviews.llvm.org/D67550
llvm-svn: 375210
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was addedllvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td