SuccessChanges

Summary

  1. [X86] Add more test cases to inline-asm-flag-output.ll. NFC (details)
  2. [DivRemPairs] Use DenseMapBase::find instead of operator[]. NFC (details)
  3. [AArch64][GlobalISel] Use the look-through constant helper for the shift s32->s64 custom legalization. (details)
  4. [Legalize][X86] Improve nnan fmin/fmax vector reduction (details)
  5. [AArch64][GlobalISel] Promote scalar G_SHL constant shift amounts to s64. (details)
Commit d78c4d9d00c15c52f0463c8dbb03945b036d53eb by craig.topper
[X86] Add more test cases to inline-asm-flag-output.ll. NFC

These are tests to make sure we are able to use the flag directly
in a conditional branch after the inline asm.
The file was modifiedllvm/test/CodeGen/X86/inline-asm-flag-output.ll
Commit 82420b4e49ff92c49c2b548bf541a5655e97d197 by i
[DivRemPairs] Use DenseMapBase::find instead of operator[]. NFC
The file was modifiedllvm/lib/Transforms/Scalar/DivRemPairs.cpp
Commit 7156938be26405156e17aa29e1c04e1afde88b04 by Amara Emerson
[AArch64][GlobalISel] Use the look-through constant helper for the shift s32->s64 custom legalization.

Almost NFC, except it catches more cases and gives a 0.1% CTMark -O0 size win.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
Commit f229bf2e12461be55446e6b08ccb931308586031 by nikita.ppv
[Legalize][X86] Improve nnan fmin/fmax vector reduction

Use +/-Inf or +/-Largest as neutral element for nnan fmin/fmax
reductions. This avoids dropping any FMF flags. Preserving the
nnan flag in particular is important to get a good lowering on X86.

Differential Revision: https://reviews.llvm.org/D87586
The file was modifiedllvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
The file was modifiedllvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll
The file was modifiedllvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
Commit 5811d723998a3abdd3cb95dc579d28f48c57c2fa by Amara Emerson
[AArch64][GlobalISel] Promote scalar G_SHL constant shift amounts to s64.

This was supposed to be done in the first place as is currently the case for
G_ASHR and G_LSHR but was forgotten when the original shift legalization
overhaul was done last year.

This was exposed because we started falling back on s32 = s32, s64 SHLs
due to a recent combiner change.

Gives a very minor (0.1%) code size -O0 improvement on consumer-typeset.
The file was modifiedllvm/test/CodeGen/AArch64/arm64-clrsb.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir