SuccessChanges

Summary

  1. [ARM] Follow AACPS standard for volatile bit-fields access width (details)
  2. [SVE] Add ISel patterns for "insert undef_nxv#f##, f##, 0" (details)
  3. [TableGen][SchedModels] Fix aliasing of SchedWriteVariant (details)
  4. [AArch64] Implement .variant_pcs directive (details)
  5. Revert "[VPlan] Use VPValue def for VPMemoryInstructionRecipe." (details)
  6. Revert "    Enable LSAN for Android" (details)
  7. [AArch64] Identify SAD pattern (details)
  8. [Test] Add test showing that SCEV cannot compute IV's range (details)
  9. [GlobalISel] Avoid making G_PTR_ADD with nullptr (details)
  10. [Fixed Point] Add fixed-point to floating point cast types and consteval. (details)
  11. [AST] Change return type of getTypeInfoInChars to a proper struct instead of std::pair. (details)
  12. [clang-tidy] Add an example for misc-unused-alias-decls (details)
  13. [ConstraintElimination] Add add/sub/and/or test cases. (details)
  14. Fix Windows/MSVC build after 6e56046f65 (details)
  15. Raise the timeout in DirectoryWatcherTest to 10 s (details)
  16. [AArch64] add cost model test for scalable vector math; NFC (details)
Commit 208987844ffa5fef636fd6bd36b4f7a7597fe520 by ties.stuij
[ARM] Follow AACPS standard for volatile bit-fields access width

This patch resumes the work of D16586.
According to the AAPCS, volatile bit-fields should
be accessed using containers of the widht of their
declarative type. In such case:
```
struct S1 {
  short a : 1;
}
```
should be accessed using load and stores of the width
(sizeof(short)), where now the compiler does only load
the minimum required width (char in this case).
However, as discussed in D16586,
that could overwrite non-volatile bit-fields, which
conflicted with C and C++ object models by creating
data race conditions that are not part of the bit-field,
e.g.
```
struct S2 {
  short a;
  int  b : 16;
}
```
Accessing `S2.b` would also access `S2.a`.

The AAPCS Release 2020Q2
(https://documentation-service.arm.com/static/5efb7fbedbdee951c1ccf186?token=)
section 8.1 Data Types, page 36, "Volatile bit-fields -
preserving number and width of container accesses" has been
updated to avoid conflict with the C++ Memory Model.
Now it reads in the note:
```
This ABI does not place any restrictions on the access widths of bit-fields where the container
overlaps with a non-bit-field member or where the container overlaps with any zero length bit-field
placed between two other bit-fields. This is because the C/C++ memory model defines these as being
separate memory locations, which can be accessed by two threads simultaneously. For this reason,
compilers must be permitted to use a narrower memory access width (including splitting the access into
multiple instructions) to avoid writing to a different memory location. For example, in
struct S { int a:24; char b; }; a write to a must not also write to the location occupied by b, this requires at least two
memory accesses in all current Arm architectures. In the same way, in struct S { int a:24; int:0; int b:8; };,
writes to a or b must not overwrite each other.
```

I've updated the patch D16586 to follow such behavior by verifying that we
only change volatile bit-field access when:
- it won't overlap with any other non-bit-field member
- we only access memory inside the bounds of the record
- avoid overlapping zero-length bit-fields.

Regarding the number of memory accesses, that should be preserved, that will
be implemented by D67399.

Reviewed By: ostannard

Differential Revision: https://reviews.llvm.org/D72932
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/test/CodeGen/aapcs-bitfield.c
The file was modifiedclang/include/clang/Basic/CodeGenOptions.def
The file was modifiedclang/lib/CodeGen/CGRecordLayout.h
The file was modifiedclang/test/CodeGen/volatile.c
The file was modifiedclang/lib/CodeGen/CGRecordLayoutBuilder.cpp
The file was modifiedclang/lib/CodeGen/CGExpr.cpp
The file was modifiedclang/test/CodeGen/bitfield-2.c
Commit 981b31c282eab6f3332c7bbed2674c10624a3fe1 by paul.walker
[SVE] Add ISel patterns for "insert undef_nxv#f##, f##, 0"

Differential Revision: https://reviews.llvm.org/D89235
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/test/CodeGen/AArch64/sve-insert-element.ll
Commit 6e56046f65c0f40215373e1cfc9ca6b788daabda by eleviant
[TableGen][SchedModels] Fix aliasing of SchedWriteVariant

Differential revision: https://reviews.llvm.org/D89114
The file was addedllvm/test/TableGen/sched-aliases.td
The file was modifiedllvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s
The file was modifiedllvm/utils/TableGen/CodeGenSchedule.cpp
The file was modifiedllvm/utils/TableGen/CodeGenSchedule.h
Commit c87bd2d8eb378d152f2b6bde4cb088ad390a676c by cullen.rhodes
[AArch64] Implement .variant_pcs directive

A dynamic linker with lazy binding support may need to handle variant
PCS function symbols specially, so an ELF symbol table marking
STO_AARCH64_VARIANT_PCS [1] was added to address this.

Function symbols that follow the vector PCS are marked via the
.variant_pcs assembler directive, which takes a single parameter
specifying the symbol name and sets the STO_AARCH64_VARIANT_PCS st_other
flag in the object file.

[1] https://github.com/ARM-software/abi-aa/blob/master/aaelf64/aaelf64.rst#st-other-values

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D89138
The file was modifiedllvm/include/llvm/BinaryFormat/ELF.h
The file was modifiedllvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
The file was addedllvm/test/MC/AArch64/directive-variant_pcs-err.s
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
The file was addedllvm/test/MC/AArch64/directive-variant_pcs.s
The file was modifiedllvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
The file was addedllvm/test/CodeGen/AArch64/variant-pcs.ll
Commit 710aceb645e7dba4de7053eef2c616311b9163d4 by Vitaly Buka
Revert "[VPlan] Use VPValue def for VPMemoryInstructionRecipe."

It introduced a memory leak.

This reverts commit 525b085a65d30a5f2ae2af38c0be252fe8d4781b.
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
The file was modifiedllvm/lib/Transforms/Vectorize/VPlanValue.h
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
Commit 25a8881b724abf7251a9278e72224af7e82cb9c2 by Vitaly Buka
Revert "    Enable LSAN for Android"

Breaks android build.
asan_malloc_dispatch_k needs memalign interceptor disabled in this patch.

This reverts commit a2291a58bf1c860d026581fee6fe96019dc25440.
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp
The file was modifiedcompiler-rt/test/lsan/TestCases/use_registers.cpp
The file was modifiedcompiler-rt/test/lsan/TestCases/disabler.cpp
The file was modifiedcompiler-rt/test/asan/TestCases/coverage-and-lsan.cpp
The file was modifiedcompiler-rt/test/lit.common.cfg.py
The file was modifiedcompiler-rt/test/lsan/TestCases/suppressions_file.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_internal_defs.h
The file was modifiedcompiler-rt/test/lsan/TestCases/Linux/use_tls_pthread_specific_static.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux.h
The file was modifiedcompiler-rt/test/lsan/TestCases/large_allocation_leak.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
The file was modifiedcompiler-rt/test/lsan/lit.common.cfg.py
The file was modifiedcompiler-rt/lib/lsan/CMakeLists.txt
The file was modifiedcompiler-rt/test/asan/lit.cfg.py
The file was modifiedcompiler-rt/test/lsan/TestCases/ignore_object.c
The file was modifiedcompiler-rt/lib/lsan/lsan_common.cpp
The file was modifiedcompiler-rt/test/lsan/TestCases/Linux/use_tls_dynamic.cpp
The file was modifiedcompiler-rt/lib/asan/tests/CMakeLists.txt
The file was modifiedcompiler-rt/test/lsan/TestCases/Linux/guard-page.c
The file was modifiedcompiler-rt/test/lsan/TestCases/Linux/cleanup_in_tsd_destructor.c
The file was modifiedcompiler-rt/test/lsan/TestCases/Linux/log-path_test.cpp
The file was modifiedcompiler-rt/lib/lsan/lsan_common.h
The file was modifiedcompiler-rt/test/lsan/TestCases/swapcontext.cpp
The file was modifiedcompiler-rt/lib/lsan/lsan_common_linux.cpp
The file was modifiedcompiler-rt/test/lsan/TestCases/disabler.c
The file was modifiedcompiler-rt/lib/asan/CMakeLists.txt
The file was modifiedcompiler-rt/cmake/config-ix.cmake
The file was modifiedcompiler-rt/test/lsan/TestCases/strace_test.cpp
The file was modifiedcompiler-rt/test/lsan/TestCases/Linux/disabler_in_tsd_destructor.c
Commit 37dce7475b2b97f27f65a80524a8ad8342e6cf7e by vinay
[AArch64] Identify SAD pattern

(ABS (SUB (EXTEND a), (EXTEND b))) to ZERO_EXTEND((UABD a, b))
(ABS (SUB (SIGN_EXTEND a), (SIGN_EXTEND b))) to ZERO_EXTEND((SABD a, b))

This partially solves the bug: https://bugs.llvm.org/show_bug.cgi?id=46888
Meta ticket: https://bugs.llvm.org/show_bug.cgi?id=46929

Differential Revision: https://reviews.llvm.org/D88742
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was modifiedllvm/test/CodeGen/AArch64/arm64-vabs.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
Commit fb2627d8d21574a0d1a81596d00953075265ac88 by mkazantsev
[Test] Add test showing that SCEV cannot compute IV's range
The file was addedllvm/test/Analysis/ScalarEvolution/no-wrap-symbolic-becount.ll
Commit 52ba4fa6aa21953a0d90c0c6e25a3ed95708d08b by Mirko.Brkusanin
[GlobalISel] Avoid making G_PTR_ADD with nullptr

When the first operand is a null pointer we can avoid making a G_PTR_ADD and
make a G_INTTOPTR with the offset operand.
This helps us avoid making add with 0 later on for targets such as AMDGPU.

Differential Revision: https://reviews.llvm.org/D87140
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-add-nullptr.mir
Commit 9fa7f48459761fa13205f4c931484b0977c35746 by bevin.hansson
[Fixed Point] Add fixed-point to floating point cast types and consteval.

Reviewed By: leonardchan

Differential Revision: https://reviews.llvm.org/D86631
The file was modifiedclang/lib/CodeGen/CGExprAgg.cpp
The file was modifiedclang/lib/CodeGen/CGExprScalar.cpp
The file was modifiedclang/lib/CodeGen/CGExpr.cpp
The file was modifiedclang/lib/AST/ExprConstant.cpp
The file was modifiedclang/include/clang/AST/OperationKinds.def
The file was modifiedclang/test/Frontend/fixed_point_conversions_const.c
The file was modifiedclang/test/Frontend/fixed_point_errors.c
The file was modifiedclang/lib/AST/Expr.cpp
The file was modifiedclang/lib/CodeGen/CGExprConstant.cpp
The file was modifiedclang/lib/Edit/RewriteObjCFoundationAPI.cpp
The file was modifiedclang/lib/StaticAnalyzer/Core/ExprEngineC.cpp
The file was modifiedclang/test/Frontend/fixed_point_unknown_conversions.c
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was modifiedclang/lib/CodeGen/CGExprComplex.cpp
Commit 101309fe048e66873cfd972c47c4b7e7f2b99f41 by bevin.hansson
[AST] Change return type of getTypeInfoInChars to a proper struct instead of std::pair.

Followup to D85191.

This changes getTypeInfoInChars to return a TypeInfoChars
struct instead of a std::pair of CharUnits. This lets the
interface match getTypeInfo more closely.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D86447
The file was modifiedclang/lib/CodeGen/CGCall.cpp
The file was modifiedclang/lib/CodeGen/CGObjC.cpp
The file was modifiedclang/lib/AST/ASTContext.cpp
The file was modifiedclang/lib/CodeGen/CGCUDANV.cpp
The file was modifiedclang/lib/CodeGen/CGRecordLayoutBuilder.cpp
The file was modifiedclang/lib/CodeGen/CGValue.h
The file was modifiedclang/lib/CodeGen/CGClass.cpp
The file was modifiedclang/lib/CodeGen/TargetInfo.cpp
The file was modifiedclang/include/clang/AST/ASTContext.h
The file was modifiedclang/lib/AST/RecordLayoutBuilder.cpp
The file was modifiedclang/lib/CodeGen/CGExprAgg.cpp
The file was modifiedclang/lib/StaticAnalyzer/Checkers/PaddingChecker.cpp
The file was modifiedclang/lib/CodeGen/CGAtomic.cpp
The file was modifiedclang/lib/CodeGen/CGBlocks.cpp
Commit 002968a320463237f0ccea754a7482b229e34cf1 by sylvestre
[clang-tidy] Add an example for misc-unused-alias-decls

Differential Revision: https://reviews.llvm.org/D89270
The file was modifiedclang-tools-extra/docs/clang-tidy/checks/misc-unused-alias-decls.rst
Commit 2322080bc3889145b7fb3c8798016467fe5e3b10 by flo
[ConstraintElimination] Add add/sub/and/or test cases.

This adds a new set of tests for upcoming constraint elimination
changes.
The file was addedllvm/test/Transforms/ConstraintElimination/add-nuw.ll
The file was addedllvm/test/Transforms/ConstraintElimination/add.ll
The file was addedllvm/test/Transforms/ConstraintElimination/and.ll
The file was addedllvm/test/Transforms/ConstraintElimination/or.ll
The file was addedllvm/test/Transforms/ConstraintElimination/sub.ll
The file was addedllvm/test/Transforms/ConstraintElimination/sub-nuw.ll
Commit 836d0addee4a2ce07d09d68484823221cbb062b7 by eleviant
Fix Windows/MSVC build after 6e56046f65

Commit 6e56046f65 may trigger SEGV in llvm-tablegen if the latter
is built with -DLLVM_OPTIMIZED_TABLEGEN=OFF. The reason of SEGV was
accessing stale memory after expansion of std::vector.
The file was modifiedllvm/utils/TableGen/CodeGenSchedule.cpp
Commit bddef54c502811fa1406d1161d4baa15b56ebc32 by hans
Raise the timeout in DirectoryWatcherTest to 10 s

After D88666, which implemented DirectoryWatcher on Windows, we're
seeing test failures on Chromium's Windows bots.

Try raising the timeout in case the test is failing due to high load on
the machine.
The file was modifiedclang/unittests/DirectoryWatcher/DirectoryWatcherTest.cpp
Commit 937d782e38d44d078342cb6358c41db7a5795d00 by spatel
[AArch64] add cost model test for scalable vector math; NFC

Testing for the various cost model "TargetCostKind" is limited,
and testing for scalable vectors is limited. The motivating
example of an intrinsic is not included here yet because that
just crashes.
The file was addedllvm/test/Analysis/CostModel/AArch64/sve-math.ll