SuccessChanges

Summary

  1. [LLD][ELF] Improve ICF for relocations to ineligible sections via "aliases" (details)
  2. [Statepoints] Remove MI limit on number of tied operands. (details)
  3. [SVE]Fix implicit TypeSize casts in EmitCheckValue (details)
  4. [AMDGPU] Minimize number of s_mov generated by copyPhysReg (details)
  5. [InstCombine] visitXor - refactor ((X^C1)>>C2)^C3 -> (X>>C2)^((C1>>C2)^C3) fold. NFCI. (details)
  6. AMDGPU: Fix verifier error on killed spill of partially undef register (details)
  7. Add "not" to an llvm-symbolizer test that expects to fail (details)
  8. [RISCV] [TableGen] Modify RISCVCompressInstEmitter.cpp to use getAllDerivedDefinitions(). (details)
  9. [TableGen] Add the !not and !xor operators. (details)
Commit 88ce27c39c5e42d8a85ac1144d2ae0fae68e8853 by andrew.ng
[LLD][ELF] Improve ICF for relocations to ineligible sections via "aliases"

ICF was not able to merge equivalent sections because of relocations to
sections ineligible for ICF that use alternative symbols, e.g. symbol
aliases or section relative relocations.

Merging in this scenario has been enabled by giving the sections that
are ineligible for ICF a unique ID, i.e. an equivalence class of their
own. This approach also provides another benefit as it improves the
hashing that is used to perform the initial equivalance grouping for
ICF. This is because the ICF ineligible sections can now contribute a
unique value towards the hashes instead of the same value of zero. This
has been seen to reduce link time with ICF by ~68% for objects compiled
with -fprofile-instr-generate.

In order to facilitate this use of a unique ID, the existing
inconsistent approach to the setting of the InputSection eqClass in ICF
has been changed so that there is a clear distinction between the
eqClass values of ICF eligible sections and those of the ineligible
sections that have a unique ID. This inconsistency could have caused
incorrect equivalence class equality in the past, although it appears
that no issues were encountered in actual use.

Differential Revision: https://reviews.llvm.org/D88830
The file was addedlld/test/ELF/icf-ineligible.s
The file was modifiedlld/ELF/ICF.cpp
Commit 8f0ddd4a1a0d2e7b8004d8c3283bddf1a2e27a18 by dantrushin
[Statepoints] Remove MI limit on number of tied operands.

After D87915 statepoint can have more than 15 tied operands.
Remove this restriction from statepoint lowering code.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
The file was addedllvm/test/CodeGen/X86/statepoint-vreg-unlimited-tied-opnds.ll
Commit 145e44bb18853bc9beeac0e64fffd9e6895e71f9 by caroline.concatto
[SVE]Fix implicit TypeSize casts in EmitCheckValue

Using TypeSize::getFixedSize() instead of relying upon the implicit
TypeSize->uint64_cast as the type is always fixed width.

Differential Revision: https://reviews.llvm.org/D89313
The file was modifiedclang/lib/CodeGen/CGExpr.cpp
Commit b70cb5020416413bf5fbfe8111891912153f3034 by carl.ritson
[AMDGPU] Minimize number of s_mov generated by copyPhysReg

Generate the minimal set of s_mov instructions required when
expanding a SGPR copy operation in copyPhysReg.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D89187
The file was modifiedllvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Commit 09be7623e4e8e81f559b1c2dc74b0b3332261491 by llvm-dev
[InstCombine] visitXor - refactor ((X^C1)>>C2)^C3 -> (X>>C2)^((C1>>C2)^C3) fold. NFCI.

This is still ConstantInt-only (scalar) but is refactored to use PatternMatch to make adding vector support in the future relatively trivial.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Commit 663f16684d1a5f129874b7be9e1f486682977bfa by Matthew.Arsenault
AMDGPU: Fix verifier error on killed spill of partially undef register

This does unfortunately end up with extra waitcnts getting inserted
that were avoided before. Ideally we would avoid the spills of these
undef components in the first place.
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-agpr.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/vgpr-spill.mir
The file was addedllvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
Commit 5e656ee48bccc73f1328db1770770acaec90a7c9 by jeremy.morse
Add "not" to an llvm-symbolizer test that expects to fail

In a7b209a6d40d77b, llvm-symbolizer was adjusted to return a failure status
code when it produced an error, to flag up DWARF parsing problems. The
test for missing PDB file is analogous, and returns a failure status now
too.

This should fix the llvm-clang-win-x-armv7l buildbot croaking:

  http://lab.llvm.org:8011/#/builders/60/builds/77
The file was modifiedllvm/test/tools/llvm-symbolizer/pdb/missing_pdb.test
Commit 81cec3943ab695c344900c1bcdeeda264ee41a30 by paul
[RISCV] [TableGen] Modify RISCVCompressInstEmitter.cpp to use getAllDerivedDefinitions().
The file was modifiedllvm/utils/TableGen/RISCVCompressInstEmitter.cpp
Commit 4767bb2c0c746eaf146927c8bcb0528bd36c7b8f by paul
[TableGen] Add the !not and !xor operators.
Update the TableGen Programmer's Reference.
The file was modifiedllvm/test/TableGen/arithmetic.td
The file was modifiedllvm/lib/TableGen/TGLexer.h
The file was modifiedllvm/test/TableGen/if.td
The file was modifiedllvm/lib/TableGen/TGLexer.cpp
The file was modifiedllvm/docs/TableGen/ProgRef.rst
The file was modifiedllvm/test/TableGen/math.td
The file was modifiedllvm/include/llvm/TableGen/Record.h
The file was modifiedllvm/lib/TableGen/TGParser.cpp
The file was modifiedllvm/lib/TableGen/Record.cpp