SuccessChanges

Summary

  1. [zorg] [PowerPC] Limit number of threads to 20 on clang-ppc64le-rhel buildbot (details)
Commit 2fc811d0946a8a2a9eb3fd3f4931d0a960593fd3 by saghir
[zorg] [PowerPC] Limit number of threads to 20 on clang-ppc64le-rhel buildbot

Earlier, we reduced the number of threads to 64 but we were still seeing
sanitizer tests failing. We experimented with the number of threads and saw
20 threads working fine for the bot. This patch reduces the number of threads
from 64 to 20 on the clang-ppc64le-rhel buildbot.

Reviewed By: #powerpc, nemanjai

Differential Revision: https://reviews.llvm.org/D88746
The file was modifiedbuildbot/osuosl/master/config/builders.py (diff)

Summary

  1. [NFC] Fix license header from D87841 (details)
  2. [mlir][standard] Fix parsing of scalar subview and canonicalize (details)
  3. [openmp][libomptarget] Include header from LLVM source tree (details)
  4. [InstCombine] InstCombineAndOrXor - refactor cast<ConstantInt> usages to PatternMatch. NFCI. (details)
  5. [InstCombine] SimplifyDemandedUseBits - xor - refactor cast<ConstantInt> usage to PatternMatch. NFCI. (details)
  6. [InstCombine] Use m_SpecificInt instead of m_APInt + comparison. NFCI. (details)
  7. [RISCV] fix a mistake in RISCVInstrInfoV.td (details)
  8. [WebAssembly] v128.load{8,16,32,64}_lane instructions (details)
  9. [LLD] [COFF] Fix a condition that was missed in 7f0e6c31c255. NFC. (details)
  10. [LLD] [COFF] Implement a GNU/ELF like -wrap option (details)
  11. [lldb] [Process/FreeBSDRemote] Initial multithreading support (details)
  12. Revert "[WebAssembly] v128.load{8,16,32,64}_lane instructions" (details)
  13. [x86] add no 'unwind' to reduce test noise; NFC (details)
  14. [libc++] Allow building libc++ on platforms without a random device (details)
  15. [libc++] NFC: Remove unused include (details)
  16. [PGO] Remove the old memop value profiling buckets. (details)
  17. [CostModel] remove cost-kind predicate for ctlz/cttz intrinsics in basic TTI implementation (details)
Commit c66e091023b87b23459ed67158fd566ebc1f8a13 by jonchesterfield
[NFC] Fix license header from D87841
The file was modifiedllvm/include/llvm/Frontend/OpenMP/OMPGridValues.h
Commit 307124535f326d75725ecf6d3f4e9e0321162e9a by herhut
[mlir][standard] Fix parsing of scalar subview and canonicalize

Parsing of a scalar subview did not create the required static_offsets attribute.
This also adds support for folding scalar subviews away.

Differential Revision: https://reviews.llvm.org/D89467
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp
The file was modifiedmlir/test/Transforms/constant-fold.mlir
The file was modifiedmlir/test/IR/core-ops.mlir
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
Commit 7d2ecef5ed11698ae106bfbf295c44d761c7f946 by jonchesterfield
[openmp][libomptarget] Include header from LLVM source tree

[openmp][libomptarget] Include header from LLVM source tree

The change is to the amdgpu plugin so is unlikely to break anything.

The point of contention is whether libomptarget can depend on LLVM.
A community discussion was cautiously not opposed yesterday.

This introduces a compile time dependency on the LLVM source tree, in this case
expressed as skipping the building of the plugin if LLVM_MAIN_INCLUDE_DIR is not
set. One the source files will #include llvm/Frontend/OpenMP/OMPGridValues.h,
instead of copy&pasting the numbers across.

For users that download the monorepo, the llvm tree is already on disk. This will
inconvenience users who download only the openmp source as a tar, as they would
now also have to download (at least a file or two) from the llvm source, if they want
to build the parts of the openmp project that (post this patch) depend on llvm.

There was interest expressed in going further - using llvm tools as part of
building libomp, or linking against llvm libraries. That seems less clear cut
an improvement and worthy of further discussion. This patch seeks only to change
policy to support openmp depending on the llvm source tree. Including in the
other direction, or using libraries / tools etc, are purposefully out of scope.

Reviewers are a best guess at interested parties, please feel free to add others

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D87841
The file was modifiedopenmp/libomptarget/plugins/amdgpu/CMakeLists.txt
The file was modifiedopenmp/libomptarget/plugins/amdgpu/src/rtl.cpp
Commit 2b45639ea0f3fcafbc647874e0902c5798903afa by llvm-dev
[InstCombine] InstCombineAndOrXor - refactor cast<ConstantInt> usages to PatternMatch. NFCI.

First step towards replacing these to add full vector support.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Commit b3330ae42c73b204f6809b808308ee90a75bc921 by llvm-dev
[InstCombine] SimplifyDemandedUseBits - xor - refactor cast<ConstantInt> usage to PatternMatch. NFCI.

First step towards replacing these to add full vector support.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
Commit 23f161662645d145a6f4621150ab5a43762f6972 by llvm-dev
[InstCombine] Use m_SpecificInt instead of m_APInt + comparison. NFCI.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Commit 2de693756fefbb8a093ffd511b6684ef132f4e11 by llvm
[RISCV] fix a mistake in RISCVInstrInfoV.td

A commit of VALUVVNoVm was wrong, fixed it.

Reviewed By: HsiangKai
Differential Revision: https://reviews.llvm.org/D88142
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoV.td
Commit 7c6bfd90ab2ddaa60de62878c8512db0645e8452 by tlively
[WebAssembly] v128.load{8,16,32,64}_lane instructions

Prototype the newly proposed load_lane instructions, as specified in
https://github.com/WebAssembly/simd/pull/350. Since these instructions are not
available to origin trial users on Chrome stable, make them opt-in by only
selecting them from intrinsics rather than normal ISel patterns. Since we only
need rough prototypes to measure performance right now, this commit does not
implement all the load and store patterns that would be necessary to make full
use of the offset immediate. However, the full suite of offset tests is included
to make it easy to track improvements in the future.

Since these are the first instructions to have a memarg immediate as well as an
additional immediate, the disassembler needed some additional hacks to be able
to parse them correctly. Making that code more principled is left as future
work.

Differential Revision: https://reviews.llvm.org/D89366
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
The file was addedllvm/test/CodeGen/WebAssembly/simd-load-lane-offset.ll
The file was modifiedllvm/include/llvm/IR/IntrinsicsWebAssembly.td
The file was modifiedllvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedllvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
The file was modifiedclang/include/clang/Basic/BuiltinsWebAssembly.def
The file was modifiedclang/test/CodeGen/builtins-wasm.c
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
The file was modifiedllvm/test/MC/WebAssembly/simd-encodings.s
Commit 9803cf57d6fe5c7189255ad74b289c2a0d4a8a6a by martin
[LLD] [COFF] Fix a condition that was missed in 7f0e6c31c255. NFC.

This should fix cases when e.g. auto import is enabled without
mingw mode in total being enabled.

Differential Revision: https://reviews.llvm.org/D89006
The file was modifiedlld/COFF/SymbolTable.cpp
Commit a012c704b5e5b60f9d2a7304d27cbc84a3619571 by martin
[LLD] [COFF] Implement a GNU/ELF like -wrap option

Add a simple forwarding option in the MinGW frontend, and implement
the private -wrap option in the COFF linker.

The feature in lld-link isn't gated by the -lldmingw option, but
the option is left as a private, undocumented option primarily
used by the MinGW driver.

The implementation is significantly based on the support for --wrap
in the ELF linker, but many small nuance details are different
between the ELF and COFF linkers, ending up with more than a few
implementation differences.

This fixes https://bugs.llvm.org/show_bug.cgi?id=47384.

Differential Revision: https://reviews.llvm.org/D89004
The file was addedlld/test/COFF/wrap-lto-2.ll
The file was modifiedlld/COFF/LTO.cpp
The file was modifiedlld/COFF/Symbols.h
The file was modifiedlld/MinGW/Driver.cpp
The file was addedlld/test/COFF/wrap.s
The file was addedlld/test/COFF/wrap-import.ll
The file was addedlld/test/COFF/wrap-lto-1.ll
The file was modifiedlld/COFF/InputFiles.h
The file was modifiedlld/COFF/MinGW.cpp
The file was modifiedlld/COFF/MinGW.h
The file was modifiedlld/COFF/Driver.cpp
The file was modifiedlld/test/MinGW/driver.test
The file was modifiedlld/COFF/Options.td
The file was modifiedlld/COFF/SymbolTable.cpp
The file was addedlld/test/COFF/wrap-with-archive.s
The file was addedlld/test/COFF/wrap-real-missing.s
The file was modifiedlld/MinGW/Options.td
The file was addedlld/test/COFF/wrap-i386.s
Commit 87d38831d909bf937039a97aa63220929d498047 by mgorny
[lldb] [Process/FreeBSDRemote] Initial multithreading support

Implement initial support for watching thread creation and termination.
Update ptrace() calls to correctly indicate requested thread.
Watchpoints are not supported yet.

This patch fixes at least multithreaded register tests.

Differential Revision: https://reviews.llvm.org/D89413
The file was modifiedlldb/source/Plugins/Process/FreeBSDRemote/NativeThreadFreeBSD.cpp
The file was modifiedlldb/source/Plugins/Process/FreeBSDRemote/NativeProcessFreeBSD.h
The file was modifiedlldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD.h
The file was modifiedlldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_x86_64.cpp
The file was modifiedlldb/source/Plugins/Process/FreeBSDRemote/NativeProcessFreeBSD.cpp
The file was modifiedlldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD.cpp
Commit 7c8385a352ba21cb388046290d93b53dc273cd9f by tlively
Revert "[WebAssembly] v128.load{8,16,32,64}_lane instructions"

This reverts commit 7c6bfd90ab2ddaa60de62878c8512db0645e8452.
The file was modifiedllvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
The file was modifiedllvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
The file was modifiedllvm/test/MC/WebAssembly/simd-encodings.s
The file was modifiedllvm/include/llvm/IR/IntrinsicsWebAssembly.td
The file was modifiedclang/test/CodeGen/builtins-wasm.c
The file was modifiedclang/include/clang/Basic/BuiltinsWebAssembly.def
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
The file was removedllvm/test/CodeGen/WebAssembly/simd-load-lane-offset.ll
Commit e9df9028a7ca67dc6198108e6ea621cb554aa3c7 by spatel
[x86] add no 'unwind' to reduce test noise; NFC

I suggested this in D89412, but the comment was missed.
The file was modifiedllvm/test/CodeGen/X86/ctpop-combine.ll
Commit e0d01294bc124211a8ffb55e69162eb34a242680 by Louis Dionne
[libc++] Allow building libc++ on platforms without a random device

Some platforms, like several embedded platforms, do not provide a source
of randomness through a random device. This commit makes it possible to
build and test libc++ for such platforms, i.e. without std::random_device.

Surprisingly, the only functionality that doesn't work on such platforms
is std::random_device itself -- everything else in <random> still works,
one just has to find alternative ways to seed the PRNGs.
The file was modifiedlibcxx/test/std/numerics/rand/rand.device/eval.pass.cpp
The file was modifiedlibcxx/utils/libcxx/test/features.py
The file was modifiedlibcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.copy_file/copy_file_large.pass.cpp
The file was modifiedlibcxx/CMakeLists.txt
The file was modifiedlibcxx/include/random
The file was modifiedlibcxx/utils/ci/buildkite-pipeline.yml
The file was addedlibcxx/test/libcxx/numerics/rand/rand.device/has-no-random-device.verify.cpp
The file was modifiedlibcxx/test/std/numerics/rand/rand.device/entropy.pass.cpp
The file was modifiedlibcxx/src/CMakeLists.txt
The file was addedlibcxx/cmake/caches/Generic-no-random_device.cmake
The file was modifiedlibcxx/test/support/filesystem_test_helper.h
The file was modifiedlibcxx/test/std/numerics/rand/rand.device/ctor.pass.cpp
The file was modifiedlibcxx/utils/ci/run-buildbot.sh
The file was modifiedlibcxx/include/__config_site.in
Commit 54f7ad2d6f520a7dba4debb7c4aa362be4dbffd0 by Louis Dionne
[libc++] NFC: Remove unused include
The file was modifiedlibcxx/src/filesystem/operations.cpp
Commit 1ebee7adf8966ad9d2885c172a18104c94667061 by yamauchi
[PGO] Remove the old memop value profiling buckets.

Following up D81682 and D83903, remove the code for the old value profiling
buckets, which have been replaced with the new, extended buckets and disabled by
default.

Also syncing InstrProfData.inc between compiler-rt and llvm.

Differential Revision: https://reviews.llvm.org/D88838
The file was modifiedcompiler-rt/lib/profile/InstrProfilingValue.c
The file was modifiedllvm/include/llvm/ProfileData/InstrProf.h
The file was modifiedllvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
The file was modifiedllvm/test/Transforms/PGOProfile/memcpy.ll
The file was modifiedllvm/test/Transforms/PGOProfile/memop_profile_funclet.ll
The file was modifiedllvm/include/llvm/Transforms/Instrumentation/InstrProfiling.h
The file was modifiedllvm/lib/Transforms/Instrumentation/PGOMemOPSizeOpt.cpp
The file was modifiedllvm/include/llvm/ProfileData/InstrProfData.inc
The file was modifiedllvm/lib/ProfileData/InstrProf.cpp
The file was modifiedcompiler-rt/include/profile/InstrProfData.inc
Commit 9f6048f83dc2be76ab97172bf1113d9fa9db7c60 by spatel
[CostModel] remove cost-kind predicate for ctlz/cttz intrinsics in basic TTI implementation

The cost modeling for intrinsics is a patchwork based on different
expectations from the callers, so it's a mess. I'm hoping to untangle
this to allow canonicalization to the new min/max intrinsics in IR.
The general goal is to remove the cost-kind restriction here in the
basic implementation class. Ie, if some intrinsic has throughput cost
of 104, assume that it has the same size, latency, and blended costs.
Effectively, an intrinsic with cost N is composed of N simple
instructions. If that's not correct, the target should provide a more
accurate override.

The x86-64 SSE2 subtarget cost diffs require explanation:

1. The scalar ctlz/cttz are assuming "BSR+XOR+CMOV" or
   "TEST+BSF+CMOV/BRANCH", so not cheap.
2. The 128-bit SSE vector width versions assume cost of 18 or 26
   (no explanation provided in the tables, but this corresponds to a
   bunch of shift/logic/compare).
3. The 512-bit vectors in the test file are scaled up by a factor of
   4 from the legal vector width costs.
4. The plain latency cost-kind is not affected in this patch because
   that calc is diverted before we get to getIntrinsicInstrCost().

Differential Revision: https://reviews.llvm.org/D89461
The file was modifiedllvm/include/llvm/CodeGen/BasicTTIImpl.h
The file was modifiedllvm/test/Analysis/CostModel/X86/intrinsic-cost-kinds.ll