1. [SCEV] Use nw flag and symbolic iteration count to sharpen ranges of AddRecs (details)
  2. [llvm-cov] Fix test cases. (details)
  3. [RISCV] Add -mtune support (details)
Commit 905101c36025fe1c8ecdf9a20cd59db036676073 by mkazantsev
[SCEV] Use nw flag and symbolic iteration count to sharpen ranges of AddRecs

We can sharpen the range of a AddRec if we know that it does not
self-wrap and know the symbolic iteration count in the loop. If we can
evaluate the value of AddRec on the last iteration and prove that at least
one its intermediate value lies between start and end, then no-wrap flag
allows us to conclude that all of them also lie between start and end. So
the estimate of range can be improved to union of ranges of start and end.

Differential Revision:
Reviewed By: efriedma
The file was modifiedllvm/include/llvm/Analysis/ScalarEvolution.h
The file was modifiedllvm/test/Transforms/IndVarSimplify/X86/eliminate-trunc.ll
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
The file was modifiedllvm/test/Analysis/ScalarEvolution/no-wrap-symbolic-becount.ll
The file was modifiedllvm/test/Transforms/IndVarSimplify/promote-iv-to-eliminate-casts.ll
Commit 19ae9b6e21e2491debeb910e2c541be9796f1b13 by zequanwu
[llvm-cov] Fix test cases.
`/dev/null` is treated as regualar file on Windows.
native_separators.c line 11 used relative path which was not correct but worked before because when `SourceFiles` is empty, it add all source files into `SourceFiles`.
The file was modifiedllvm/test/tools/llvm-cov/native_separators.c
The file was modifiedllvm/test/tools/llvm-cov/warnings.h
Commit cfa7094e49cfb7e37a84c0aa57c85c64c0581d17 by kito.cheng
[RISCV] Add -mtune support

- The goal of this patch is improve option compatible with RISCV-V GCC,
   -mcpu support on GCC side will sent patch in next few days.

- -mtune only affect the pipeline model and non-arch/extension related
   target feature, e.g. instruction fusion; in td file it called
   TuneFeatures, which is introduced by X86 back-end[1].

- -mtune accept all valid option for -mcpu and extra alias processor
   option, e.g. `generic`, `rocket` and `sifive-7-series`, the purpose is
   option compatible with RISCV-V GCC.

- Processor alias for -mtune will resolve according the current target arch,
   rv32 or rv64, e.g. `rocket` will resolve to `rocket-rv32` or `rocket-rv64`.

- Interaction between -mcpu and -mtune:
   * -mtune has higher priority than -mcpu for pipeline model and


Reviewed By: luismarques

Differential Revision:
The file was modifiedllvm/include/llvm/Support/TargetParser.h
The file was modifiedclang/test/Misc/target-invalid-cpu-note.c
The file was modifiedllvm/lib/Target/RISCV/RISCVTargetMachine.cpp
The file was modifiedllvm/lib/Support/TargetParser.cpp
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVSubtarget.h
The file was modifiedclang/lib/Basic/Targets/RISCV.cpp
The file was modifiedclang/lib/Basic/Targets/RISCV.h
The file was modifiedllvm/include/llvm/Support/RISCVTargetParser.def
The file was modifiedclang/test/Driver/riscv-cpus.c
The file was modifiedclang/include/clang/Driver/
The file was modifiedllvm/lib/Target/RISCV/RISCVSubtarget.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVAsmPrinter.cpp