FailedChanges

Summary

  1. [SLP] Better estimate cost of no-op extracts on target vectors. (details)
  2. Always emit error for wrong interfaces to scalable vectors, unless cmdline flag is passed. (details)
  3. [gn build] Port 0f7bbbc481e2 (details)
  4. [X86][SSE] isHorizontalBinOp - use getTargetShuffleInputs helper (details)
  5. [LLDB] Skip TestLoadUsingLazyBind.py on arm/linux (details)
  6. [RISCV] Test llvm.experimental.vector.insert intrinsics on RV32 (details)
  7. [InstCombine] Fix out-of-bounds ashr(shl) optimization (details)
  8. [mlir][spirv] Add utilities for push constant value (details)
  9. [NFC][SVE] Use SVE_4_Op_Imm_Pat for sve_intx_dot_by_indexed_elem (details)
  10. [AArch64][SVE] Lowering sve.dot to DOT node (details)
  11. [NFC][SVE] update sve-intrinsics-int-arith.ll under update_llc_test_checks.py (details)
Commit 0f3230390b8becb59362963b8be630b3e32541b1 by flo
[SLP] Better estimate cost of no-op extracts on target vectors.

The motivation for this patch is to better estimate the cost of
extracelement instructions in cases were they are going to be free,
because the source vector can be used directly.

A simple example is

    %v1.lane.0 = extractelement <2 x double> %v.1, i32 0
    %v1.lane.1 = extractelement <2 x double> %v.1, i32 1

    %a.lane.0 = fmul double %v1.lane.0, %x
    %a.lane.1 = fmul double %v1.lane.1, %y

Currently we only consider the extracts free, if there are no other
users.

In this particular case, on AArch64 which can fit <2 x double> in a
vector register, the extracts should be free, independently of other
users, because the source vector of the extracts will be in a vector
register directly, so it should be free to use the vector directly.

The SLP vectorized version of noop_extracts_9_lanes is 30%-50% faster on
certain AArch64 CPUs.

It looks like this does not impact any code in
SPEC2000/SPEC2006/MultiSource both on X86 and AArch64 with -O3 -flto.

This originally regressed after D80773, so if there's a better
alternative to explore, I'd be more than happy to do that.

Reviewed By: ABataev

Differential Revision: https://reviews.llvm.org/D99719
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-fp-inseltpoison.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-fp.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/vectorize-free-extracts-inserts.ll
Commit 0f7bbbc481e20a152c74bc315f8995b62d54c8c0 by sander.desmalen
Always emit error for wrong interfaces to scalable vectors, unless cmdline flag is passed.

In order to bring up scalable vector support in LLVM incrementally,
we introduced behaviour to emit a warning, instead of an error, when
asking the wrong question of a scalable vector, like asking for the
fixed number of elements.

This patch puts that behaviour under a flag. The default behaviour is
that the compiler will always error, which means that all LLVM unit
tests and regression tests will now fail when a code-path is taken that
still uses the wrong interface.

The behaviour to demote an error to a warning can be individually enabled
for tools that want to support experimental use of scalable vectors.
This patch enables that behaviour when driving compilation from Clang.
This means that for users who want to try out scalable-vector support,
fixed-width codegen support, or build user-code with scalable vector
intrinsics, Clang will not crash and burn when the compiler encounters
such a case.

This allows us to do away with the following pattern in many of the SVE tests:
  RUN: .... 2>%t
  RUN: cat %t | FileCheck --check-prefix=WARN
  WARN-NOT: warning: ...

The behaviour to emit warnings is only temporary and we expect this flag
to be removed in the future when scalable vector support is more stable.

This patch also has fixes the following tests:
unittests:
   ScalableVectorMVTsTest.SizeQueries
   SelectionDAGAddressAnalysisTest.unknownSizeFrameObjects
   AArch64SelectionDAGTest.computeKnownBitsSVE_ZERO_EXTEND_VECTOR_INREG

regression tests:
   Transforms/InstCombine/vscale_gep.ll

Reviewed By: paulwalker-arm, ctetreau

Differential Revision: https://reviews.llvm.org/D98856
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp
The file was modifiedllvm/unittests/CodeGen/ScalableVectorMVTsTest.cpp
The file was modifiedllvm/include/llvm/Support/TypeSize.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was addedllvm/lib/Support/TypeSize.cpp
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedllvm/lib/Support/CMakeLists.txt
The file was modifiedllvm/include/llvm/CodeGen/ValueTypes.h
Commit b0c32199a6dd85f5e50083aaf51242a803576a01 by llvmgnsyncbot
[gn build] Port 0f7bbbc481e2
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn
Commit 500969f1d0b1d92d7c4ccfb6bf8807de96b7e4a0 by llvm-dev
[X86][SSE] isHorizontalBinOp - use getTargetShuffleInputs helper

Use the getTargetShuffleInputs helper for all shuffle decoding
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 455973162cb98d440753fcff923793d24de00c83 by omair.javaid
[LLDB] Skip TestLoadUsingLazyBind.py on arm/linux
The file was modifiedlldb/test/API/functionalities/load_lazy/TestLoadUsingLazyBind.py
Commit 411673e769acfc63a75b9e643775b6c7f27f256f by fraser
[RISCV] Test llvm.experimental.vector.insert intrinsics on RV32

RV32 is able to use the llvm.experimental.vector.insert intrinsics too.
This patch ensures they're tested.

Reviewed By: khchen, asb

Differential Revision: https://reviews.llvm.org/D99655
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
Commit b82b305cf94a57a7e0e72f576b85aaa136a505c3 by jeroen.dobbelaere
[InstCombine] Fix out-of-bounds ashr(shl) optimization

This fixes a crash found by the oss fuzzer and reported by @fhahn.
The suggestion of @RKSimon seems to be the correct fix here. (See D91343).

The oss fuzz report can be found here: https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=32759

Reviewed By: lebedev.ri

Differential Revision: https://reviews.llvm.org/D99792
The file was addedllvm/test/Transforms/InstCombine/oss_fuzz_32759.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
Commit 6dd07fa513cd3b806e7f852bb98e5c34bab11b36 by antiagainst
[mlir][spirv] Add utilities for push constant value

This commit add utility functions for creating push constant
storage variable and loading values from it.

Along the way, performs some clean up:

* Deleted `setABIAttrs`, which is just a 4-liner function
  with one user.
* Moved `SPIRVConverstionTarget` into `mlir` namespace,
  to be consistent with `SPIRVTypeConverter` and
  `LLVMConversionTarget`.

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D99725
The file was modifiedmlir/lib/Conversion/GPUToSPIRV/GPUToSPIRV.cpp
The file was modifiedmlir/lib/Conversion/StandardToSPIRV/StandardToSPIRVPass.cpp
The file was modifiedmlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
The file was modifiedmlir/lib/Conversion/LinalgToSPIRV/LinalgToSPIRVPass.cpp
The file was modifiedmlir/test/lib/Dialect/SPIRV/TestAvailability.cpp
The file was modifiedmlir/lib/Conversion/SCFToSPIRV/SCFToSPIRVPass.cpp
The file was modifiedmlir/lib/Conversion/GPUToSPIRV/GPUToSPIRVPass.cpp
The file was modifiedmlir/lib/Conversion/VectorToSPIRV/VectorToSPIRVPass.cpp
The file was modifiedmlir/docs/Dialects/SPIR-V.md
The file was modifiedmlir/include/mlir/Dialect/SPIRV/Transforms/SPIRVConversion.h
Commit ab3c5fb28259a3b768d9774baddaab58c7e51438 by JunMa
[NFC][SVE] Use SVE_4_Op_Imm_Pat for sve_intx_dot_by_indexed_elem
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
Commit 274ac9d40e79f25ac8c928732875708b5bac8f09 by JunMa
[AArch64][SVE] Lowering sve.dot to DOT node

Differential Revision: https://reviews.llvm.org/D99699
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-int-arith.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Commit 2dfa2c0ea02d0777fb971c2519b0b9014e72b547 by JunMa
[NFC][SVE] update sve-intrinsics-int-arith.ll under update_llc_test_checks.py
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-int-arith.ll