1. [OpenMP][OMPIRBuilder] Introducing the `OMPBuilderCBHelpers` helper class (details)
  2. [Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1 (details)
  3. [x86] add test for uint->fp with unsafe-fp-math (PR43609); NFC (details)
  4. [AMDGPU] Update AMDGPUUsage with DWARF proposal (details)
  5. [IndVarSimply] Fix assert/release build difference. (details)
  6. [AMDGPU] AMDGPUUsage define call convention ABI (details)
  7. [libc++] Fixes backreferences for extended grammar. (details)
  8. [libc++] reduce <complex> parsing time (details)
Commit ba3f863dfb9c5f9bf5e6fdca2198b609df3b7761 by johannes
[OpenMP][OMPIRBuilder] Introducing the `OMPBuilderCBHelpers` helper class

This patch introduces a new helper class `OMPBuilderCBHelpers`,
which will contain all reusable C/C++ language specific function-
alities required by the `OMPIRBuilder`.

Initially, this helper class contains the body and finalization
codegen functionalities implemented using callbacks which were
moved here for reusability among the different directives
implemented in the `OMPIRBuilder`, along with RAIIs for preserving
state prior to emitting outlined and/or inlined OpenMP regions.

In the future this helper class will also contain all the different
call backs required by OpenMP clauses/variable privatization.

Reviewed By: jdoerfert

Differential Revision:
The file was modifiedclang/lib/CodeGen/CodeGenFunction.h
The file was modifiedclang/lib/CodeGen/CGStmtOpenMP.cpp
The file was modifiedclang/test/OpenMP/cancel_codegen.cpp
Commit b1d47467e26142e6029e9ec7ca5c42645ffaa7bb by kparzysz
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1

This commit removes the artificial types <512 x i1> and <1024 x i1>
from HVX intrinsics, and makes v512i1 and v1024i1 no longer legal on

It may cause existing bitcode files to become invalid.

* Converting between vector predicates and vector registers must be
  done explicitly via vandvrt/vandqrt instructions (their intrinsics),
  i.e. (for 64-byte mode):
    %Q = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %V, i32 -1)
    %V = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %Q, i32 -1)

  The conversion intrinsics are:
    declare  <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32)
    declare <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32>, i32)
    declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32)
    declare <32 x i32> @llvm.hexagon.V6.vandqrt.128B(<128 x i1>, i32)
  They are all pure.

* Vector predicate values cannot be loaded/stored directly. This directly
  reflects the architecture restriction. Loading and storing or vector
  predicates must be done indirectly via vector registers and explicit
  conversions via vandvrt/vandqrt instructions.
The file was modifiedllvm/include/llvm/IR/
The file was modifiedclang/test/CodeGen/builtins-hexagon-v66-128B.c
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
The file was addedclang/include/clang/Basic/BuiltinsHexagonMapCustomDep.def
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedllvm/test/CodeGen/Hexagon/v60-vecpred-spill.ll
The file was modifiedllvm/test/CodeGen/Hexagon/vecPred2Vec.ll
The file was modifiedclang/test/CodeGen/builtins-hexagon-v66.c
The file was modifiedllvm/lib/Target/Hexagon/
The file was modifiedllvm/test/CodeGen/Hexagon/intrinsics/v65.ll
The file was modifiedllvm/test/CodeGen/Hexagon/early-if-vecpred.ll
The file was modifiedllvm/test/CodeGen/Hexagon/hvx-dual-output.ll
The file was modifiedclang/include/clang/Basic/BuiltinsHexagonDep.def
The file was modifiedllvm/test/CodeGen/Hexagon/split-vecpred.ll
The file was modifiedllvm/test/CodeGen/Hexagon/intrinsics/v65-gather-double.ll
The file was modifiedllvm/test/CodeGen/Hexagon/v62-inlasm4.ll
The file was modifiedllvm/test/CodeGen/Hexagon/intrinsics/byte-store.ll
The file was modifiedllvm/test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll
The file was modifiedllvm/test/CodeGen/Hexagon/v6vect-pred2.ll
The file was modifiedllvm/test/CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll
The file was modifiedllvm/test/CodeGen/Hexagon/late_instr.ll
The file was modifiedllvm/test/CodeGen/Hexagon/v60small.ll
The file was modifiedllvm/test/CodeGen/Hexagon/intrinsics/v65-scatter-double.ll
The file was modifiedllvm/test/CodeGen/Hexagon/v6-inlasm4.ll
The file was modifiedllvm/test/CodeGen/Hexagon/vect-downscale.ll
The file was modifiedllvm/test/CodeGen/Hexagon/reg-scavengebug-4.ll
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLowering.cpp
The file was modifiedllvm/test/CodeGen/Hexagon/hvx-dbl-dual-output.ll
The file was modifiedllvm/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll
The file was modifiedllvm/test/CodeGen/Hexagon/intrinsics/v65-gather.ll
The file was modifiedclang/test/CodeGen/builtins-hvx64.c
The file was modifiedllvm/test/CodeGen/Hexagon/swp-sigma.ll
The file was modifiedllvm/test/CodeGen/Hexagon/vselect-pseudo.ll
The file was modifiedllvm/lib/Target/Hexagon/
The file was modifiedllvm/test/CodeGen/Hexagon/peephole-move-phi.ll
The file was modifiedclang/test/CodeGen/builtins-hvx128.c
The file was modifiedllvm/test/CodeGen/Hexagon/v6-unaligned-spill.ll
The file was modifiedllvm/test/CodeGen/Hexagon/v6vect-spill-kill.ll
The file was modifiedllvm/test/CodeGen/Hexagon/hvx-byte-store-double.ll
The file was modifiedllvm/include/llvm/IR/
The file was modifiedllvm/test/CodeGen/Hexagon/intrinsics-v60-vcmp.ll
The file was modifiedllvm/test/CodeGen/Hexagon/bug-aa4463-ifconv-vecpred.ll
The file was modifiedclang/include/clang/Basic/BuiltinsHexagon.def
The file was modifiedllvm/lib/Target/Hexagon/
The file was modifiedllvm/test/CodeGen/Hexagon/v60-vsel1.ll
The file was modifiedllvm/test/CodeGen/Hexagon/intrinsics/v65-scatter.ll
The file was modifiedllvm/test/CodeGen/Hexagon/inline-asm-qv.ll
The file was modifiedllvm/test/CodeGen/Hexagon/hvx-byte-store.ll
The file was modifiedllvm/test/CodeGen/Hexagon/v6-vecpred-copy.ll
The file was modifiedllvm/test/CodeGen/Hexagon/v60Intrins.ll
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonSubtarget.h
The file was modifiedllvm/test/CodeGen/Hexagon/v60_sort16.ll
The file was modifiedllvm/test/CodeGen/Hexagon/v60-vsel2.ll
The file was modifiedllvm/test/CodeGen/Hexagon/vector-align.ll
The file was modifiedllvm/test/CodeGen/Hexagon/reg-scavengebug-2.ll
The file was modifiedllvm/test/CodeGen/Hexagon/intrinsics-v60-alu.ll
The file was modifiedllvm/test/CodeGen/Hexagon/intrinsics-v60-misc.ll
The file was modifiedclang/include/clang/module.modulemap
The file was modifiedllvm/test/CodeGen/Hexagon/swp-prolog-phi.ll
The file was modifiedclang/lib/Basic/Targets/Hexagon.h
The file was modifiedllvm/test/CodeGen/Hexagon/inline-asm-vecpred128.ll
The file was modifiedllvm/test/CodeGen/Hexagon/intrinsics/byte-store-double.ll
The file was modifiedllvm/test/CodeGen/Hexagon/vec-pred-spill1.ll
The file was modifiedllvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll
The file was modifiedllvm/test/CodeGen/Hexagon/v6-spill1.ll
The file was modifiedllvm/test/CodeGen/Hexagon/v6vect-dbl-spill.ll
The file was modifiedllvm/test/CodeGen/Hexagon/reg-scavengebug-3.ll
Commit 2ade59ec9430b23d4d42c8197b71e441a0b32773 by spatel
[x86] add test for uint->fp with unsafe-fp-math (PR43609); NFC
The file was modifiedllvm/test/CodeGen/X86/vec_int_to_fp.ll
Commit f5678d4a6a602bd966570b6f9fdd9aa0de5855b8 by Tony.Tye
[AMDGPU] Update AMDGPUUsage with DWARF proposal

- Add AMDGPU DWARF proposal.
- Add references for gfx10 ISA and SemVer.

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, aprantl, dstuttard, tpr, jfb, dmgreen, llvm-commits

Tags: #llvm

Differential Revision:
The file was modifiedllvm/docs/AMDGPUUsage.rst
Commit e4d20ec8add39209972e55a71c327fa5b4fc4400 by llvm-project
[IndVarSimply] Fix assert/release build difference.

In builds with assertions enabled (!NDEBUG), IndVarSimplify does an
additional query to ScalarEvolution which may change future SCEV queries
since it fills the internal cache differently. The result is actually
only used with the -verify-indvars command line option. We fix the issue
by only calling SE->getBackedgeTakenCount(L) if -verify-indvars is
enabled such that only -verify-indvars shows the behavior, but not debug
builds themselves. Also add a remark to the description of
-verify-indvars about this behavior.


Differential Revision:
The file was addedllvm/test/Transforms/IndVarSimplify/deterministic-scev-verify.ll
The file was modifiedllvm/lib/Transforms/Scalar/IndVarSimplify.cpp
Commit 788e74ce29c9b2dfd6b392b03b7b829f01d637a7 by Tony.Tye
[AMDGPU] AMDGPUUsage define call convention ABI

Reviewers: scott.linder, arsenm, b-sumner

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, kerbowa, llvm-commits

Tags: #llvm

Differential Revision:
The file was modifiedllvm/docs/AMDGPUUsage.rst
Commit 6ba2d7b166c2e07dfc8328a8253276710619b1fe by Louis Dionne
[libc++] Fixes backreferences for extended grammar.

The regex backreferences were not properly parsed and used when using
the extended grammar. This change parses them. The issue was found while
working on PR34297.

Thanks to Mark de Wever for the patch!

Differential Revision:
The file was modifiedlibcxx/include/regex
The file was modifiedlibcxx/test/std/re/re.alg/re.alg.match/extended.pass.cpp
The file was modifiedlibcxx/test/std/re/re.alg/
Commit c3478eff7a65d6a77b34e756eabc7176a2b422e8 by Louis Dionne
[libc++] reduce <complex> parsing time

Instead of including <ios> for ios_base::failbit, simply get failbit
member of the template argument. Print directly to a stream instead
of using intermediate ostringstream.

    Parsing time: 874ms -> 164ms (-81%)

Thanks to Nikita Kniazev for the patch!

Differential Revision:
The file was modifiedlibcxx/include/complex