SuccessChanges

Summary

  1. [X86] combineX86ShuffleChain - pull out repeated RootVT.getSizeInBits() calls. NFCI. (details)
  2. [X86] Use const APInt& in for-range loop to avoid unnecessary copies. NFCI. (details)
  3. [X86] Pass SDLoc by const reference. NFCI. (details)
  4. [X86] Use const APInt& in for-range loop to avoid unnecessary copies. NFCI. (details)
  5. [DWARFYAML][debug_aranges] Make the 'Descriptors' field optional. (details)
  6. [InstSimplify] Reduce code duplication in icmp of binop folds (NFC) (details)
  7. Revert "[Attributor] AAPotentialValues Interface" (details)
  8. Remove unused param tag to fix Wdocumentation warning. NFC. (details)
  9. [DAG] TargetLowering::LowerAsmOutputForConstraint - pass SDLoc as const& (details)
  10. [DAG] TargetLowering::expandMUL_LOHI - pass SDLoc as const& (details)
  11. Use merge null and isa<> tests into isa_and_nonnull<>. NFCI. (details)
  12. X86InstrInfo.cpp - fix include ordering. NFCI. (details)
  13. GlobalISel: Implement bitcast action for G_EXTRACT_VECTOR_ELEMENT (details)
  14. [InstSimplify] add tests for max(max x,y), x) and variants; NFC (details)
  15. [InstSimplify] fold max (max X, Y), X --> max X, Y (details)
  16. [IR] Add IRBuilderBase::CreateVectorSplat(ElementCount EC) variant (details)
Commit 2700311cce99d2a3ef45002e32b8832b88214f7d by llvm-dev
[X86] combineX86ShuffleChain - pull out repeated RootVT.getSizeInBits() calls. NFCI.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 3f276840b6f8b2624f0bbeb6097d8049d27d5ca0 by llvm-dev
[X86] Use const APInt& in for-range loop to avoid unnecessary copies. NFCI.

Fixes clang-tidy warning.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit d7e261674141ce42557c57f01869d27f0aecf6ee by llvm-dev
[X86] Pass SDLoc by const reference. NFCI.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 20fbbbc583f4d7a35c380b0b88ea96cff0237856 by llvm-dev
[X86] Use const APInt& in for-range loop to avoid unnecessary copies. NFCI.

Fixes clang-tidy warning.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 8d1b9505f24aad4015d435cc9f23f77f7ff703f8 by Xing
[DWARFYAML][debug_aranges] Make the 'Descriptors' field optional.
The file was modifiedllvm/lib/ObjectYAML/DWARFYAML.cpp
Commit a0addbb4ec8c7bf791139699d46b08413c46eed7 by nikita.ppv
[InstSimplify] Reduce code duplication in icmp of binop folds (NFC)

For folds where we check for the binop on both the LHS and RHS,
extract a function that expects it on the LHS and call it with
swapped order.
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp
Commit 376b64926b70c8b146caaf397616fb681ae329ca by okuraofvegetable
Revert "[Attributor] AAPotentialValues Interface"

The commit cause build failure.
The file was modifiedllvm/include/llvm/Transforms/IPO/Attributor.h
The file was modifiedllvm/lib/Transforms/IPO/Attributor.cpp
The file was modifiedllvm/lib/Transforms/IPO/AttributorAttributes.cpp
The file was removedllvm/test/Transforms/Attributor/potential.ll
The file was modifiedllvm/include/llvm/ADT/APInt.h
The file was modifiedllvm/lib/IR/LLVMContextImpl.h
Commit 90dab1aece7100ace855321162c0d2a09b31c1b3 by llvm-dev
Remove unused param tag to fix Wdocumentation warning. NFC.
The file was modifiedclang/lib/Parse/ParseOpenMP.cpp
Commit d14a22da5e437dfbf5fe96a6586cec2153f36861 by llvm-dev
[DAG] TargetLowering::LowerAsmOutputForConstraint - pass SDLoc as const&

Try to be more consistent with the SDLoc param in the TargetLowering methods.
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.h
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit b8ffbf0e02e24d7be3017c8ee5f17dab9e39719f by llvm-dev
[DAG] TargetLowering::expandMUL_LOHI - pass SDLoc as const&

Try to be more consistent with the SDLoc param in the TargetLowering methods.

This also exposes an issue where we were passing a SDNode as a SDLoc, relying on the implicit SDLoc(SDNode) constructor.
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit 7dd4f03595d3687cab555d538c82a41f1c1043ce by llvm-dev
Use merge null and isa<> tests into isa_and_nonnull<>. NFCI.
The file was modifiedllvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
Commit 00d0f354f26dc725ee1ce756df383557eeb44c65 by llvm-dev
X86InstrInfo.cpp - fix include ordering. NFCI.
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.cpp
Commit 212570abcf755b8577a7aec80777503232d36d77 by Matthew.Arsenault
GlobalISel: Implement bitcast action for G_EXTRACT_VECTOR_ELEMENT

For AMDGPU, vectors with elements < 32 bits should be indexed in
32-bit elements and the desired bits extracted from there. For
elements > 64-bits, these should be reduce to 64/32 elements to enable
the normal dynamic indexing paths.

In the dynamic index cases, this produces shorter code most of the
time. This does immediately regress the constant index cases, but this
should be fixed once we have the most basic of shift combines.

The element size > 64 case is pretty much ported from the exisiting
DAG implementation for extract element promote. The increasing element
size case is new.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll
Commit e37987563ad194c41125ce836cc04df57737c698 by spatel
[InstSimplify] add tests for max(max x,y), x) and variants; NFC
The file was modifiedllvm/test/Transforms/InstSimplify/maxmin_intrinsics.ll
Commit 4abc69c6f541e7726913c9b0940728b1e0024b4a by spatel
[InstSimplify] fold max (max X, Y), X --> max X, Y

https://alive2.llvm.org/ce/z/VGgG3M
The file was modifiedllvm/test/Transforms/InstSimplify/maxmin_intrinsics.ll
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp
Commit e20223672100ed4826827412b80a605c759538da by llvm-dev
[IR] Add IRBuilderBase::CreateVectorSplat(ElementCount EC) variant

As discussed on D81500, this adds a more general ElementCount variant of the build helper and converts the (non-scalable) unsigned NumElts variant to use it internally.
The file was modifiedllvm/include/llvm/IR/IRBuilder.h
The file was modifiedllvm/unittests/Analysis/VectorUtilsTest.cpp
The file was modifiedllvm/lib/IR/IRBuilder.cpp