SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [mlir] Fix translation of splat constants to LLVM IR (details)
  2. [ARM][MVE] Disallow VPSEL for tail predication (details)
  3. [SelectionDAG] ComputeKnownBits - merge (details)
  4. [X86][SSE] Add add(shl(and(x,c1),c2),c3) test case with non-uniform (details)
  5. [ARM][Thumb2] Fix ADD/SUB invalid writes to SP (details)
  6. [ARM][LowOverheadLoops] Change predicate inspection (details)
  7. [SelectionDAG] ComputeKnownBits - merge (details)
Commit d6ea8ff0d74bfe5cd181ccfe91c2c300c5f7a35d by zinenko
[mlir] Fix translation of splat constants to LLVM IR
Summary: When converting splat constants for nested sequential LLVM IR
types wrapped in MLIR, the constant conversion was erroneously assuming
it was always possible to recursively construct a constant of a
sequential type given only one value. Instead, wait until all sequential
types are unpacked recursively before constructing a scalar constant and
wrapping it into the surrounding sequential type.
Subscribers: mehdi_amini, rriddle, jpienaar, burmako, shauheen,
antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, aartbik,
liufengdb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72688
The file was modifiedmlir/lib/Target/LLVMIR/ModuleTranslation.cpp
The file was modifiedmlir/test/Target/llvmir.mlir
Commit e73b20c57dc7a8c847ebadeb7e19c08ec84f5bd7 by sam.parker
[ARM][MVE] Disallow VPSEL for tail predication
Due to the current way that we collect predicated instructions, we can't
easily handle vpsel in tail predicated loops. There are a couple of
issues: 1) It will use the VPR as a predicate operand, but doesn't have
to be
  instead a VPT block, which means we can assert while building up
  the VPT block because we don't find another VPST to being a new
  one. 2) VPSEL still requires a VPR operand even after tail
predicating,
  which means we can't remove it unless there is another
  instruction, such as vcmp, that can provide the VPR def.
The first issue should be a relatively simple fix in the logic of the
LowOverheadLoops pass, whereas the second will require us to represent
the 'implicit' tail predication with an explicit value.
Differential Revision: https://reviews.llvm.org/D72629
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir
The file was modifiedllvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
Commit a43b0065c5c78eba3fb83881fb628f5b8182db64 by llvm-dev
[SelectionDAG] ComputeKnownBits - merge
getValidMinimumShiftAmountConstant() and generic ISD::SRL handling.
As mentioned by @nikic on rGef5debac4302 (although that was just about
SHL), we can merge the guaranteed top zero bits from the shifted value,
and then, if a min shift amount is known, zero out the top bits as well.
SHL tests / handling will be added in a follow up patch.
The file was modifiedllvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
The file was modifiedllvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Commit fd42a4ac7a69adb92f87c7fa927509f177dcc6ca by llvm-dev
[X86][SSE] Add add(shl(and(x,c1),c2),c3) test case with non-uniform
shift value
As mentioned by @nikic on rGef5debac4302, we should merge the guaranteed
top zero bits from the shifted value and min shift amount code so they
can both set the high bits to zero.
The file was modifiedllvm/test/CodeGen/X86/combine-shl.ll
Commit d94d079a6a5b12156e4b818c8ba46eb143f335b9 by diogo.sampaio
[ARM][Thumb2] Fix ADD/SUB invalid writes to SP
Summary: This patch fixes pr23772  [ARM] r226200 can emit illegal thumb2
instruction: "sub sp, r12, #80". The violation was that SUB and ADD
(reg, immediate) instructions can only write to SP if the source
register is also SP. So the above instructions was unpredictable. To
enforce that the instruction t2(ADD|SUB)ri does not write to SP we now
enforce the destination register to be rGPR (That exclude PC and SP).
Different than the ARM specification, that defines one instruction that
can read from SP, and one that can't, here we inserted one that can't
write to SP, and other that can only write to SP as to reuse most of the
hard-coded size optimizations. When performing this change, it uncovered
that emitting Thumb2 Reg plus Immediate could not emit all variants of
ADD SP, SP #imm instructions before so it was refactored to be able to.
(see test/CodeGen/Thumb2/mve-stacksplot.mir where we use a subw sp, sp,
Imm12 variant ) It also uncovered a disassembly issue of adr.w
instructions, that were only written as SUBW instructions (see
llvm/test/MC/Disassembler/ARM/thumb2.txt).
Reviewers: eli.friedman, dmgreen, carwil, olista01, efriedma, andreadb
Reviewed By: efriedma
Subscribers: gbedwell, john.brawn, efriedma, ostannard, kristof.beyls,
hiraditya, dmgreen, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70680
The file was modifiedllvm/test/MC/ARM/invalid-addsub.s
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
The file was modifiedllvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir
The file was modifiedllvm/lib/Target/ARM/Thumb2InstrInfo.cpp
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/thumb-select-arithmetic-ops.mir
The file was addedllvm/test/CodeGen/Thumb2/t2peephole-t2ADDrr-to-t2ADDri.ll
The file was modifiedllvm/test/MC/ARM/thumb-diagnostics.s
The file was modifiedllvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
The file was modifiedllvm/lib/Target/ARM/ARMAsmPrinter.cpp
The file was modifiedllvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/peephole-addsub.mir
The file was addedllvm/test/CodeGen/Thumb2/bug-subw.ll
The file was modifiedllvm/lib/Target/ARM/ARMInstrThumb2.td
The file was modifiedllvm/test/MC/Disassembler/ARM/thumb-tests.txt
The file was modifiedllvm/test/MC/ARM/basic-thumb2-instructions.s
The file was modifiedllvm/test/MC/Disassembler/ARM/invalid-thumbv7.txt
The file was modifiedllvm/test/CodeGen/Thumb2/mve-stacksplot.mir
The file was modifiedllvm/test/CodeGen/Thumb2/fp16-stacksplot.mir
The file was modifiedllvm/test/MC/Disassembler/ARM/thumb2-v8.txt
The file was modifiedllvm/test/MC/Disassembler/ARM/thumb2.txt
The file was modifiedllvm/test/MC/ARM/negative-immediates.s
The file was modifiedllvm/test/MC/ARM/register-token-source-loc.s
The file was addedllvm/test/tools/llvm-mca/ARM/simple-cortex-m33.s
The file was modifiedllvm/test/CodeGen/Thumb2/peephole-cmp.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir
Commit bad6032bc15fa8d16b67b86ef2b2fe48724e756e by sam.parker
[ARM][LowOverheadLoops] Change predicate inspection
Use the already provided helper function to get the operand type so that
we can detect whether the vpr is being used as a predicate or not. Also
use existing helpers to get the predicate indices when we converting the
vpt blocks. This enables us to support both types of vpr predicate
operand.
Differential Revision: https://reviews.llvm.org/D72504
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vmaxmin_vpred_r.mir
The file was modifiedllvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
Commit c05a11108b9a9deb266c3c1758677462df61e05e by llvm-dev
[SelectionDAG] ComputeKnownBits - merge
getValidMinimumShiftAmountConstant() and generic ISD::SHL handling.
As mentioned by @nikic on rGef5debac4302, we can merge the guaranteed
bottom zero bits from the shifted value, and then, if a min shift amount
is known, zero out the bottom bits as well.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/test/CodeGen/X86/combine-shl.ll