SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. Revert "[Loop Peeling] Add possibility to enable peeling on loop nests." (details)
  2. [ELF] Decrease alignment of ThunkSection on 64-bit targets from 8 to 4 (details)
  3. [Hexagon] Add a target feature to disable compound instructions (details)
Commit c87982b46701155926ca2c2bf07cbda3d3bade7b by arkady.shlykov
Revert "[Loop Peeling] Add possibility to enable peeling on loop nests."
This reverts commit 3f3017e because there's a failure on
peel-loop-nests.ll with LLVM_ENABLE_EXPENSIVE_CHECKS on.
Differential Revision: https://reviews.llvm.org/D70304
The file was removedllvm/test/Transforms/LoopUnroll/peel-loop-nests.ll
The file was modifiedllvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
The file was modifiedllvm/lib/Transforms/Utils/LoopUnrollPeel.cpp
The file was modifiedllvm/test/Transforms/LoopUnroll/peel-loop-conditions.ll
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfo.h
Commit 870094decfc9fe80c8e0a6405421b7d09b97b02b by maskray
[ELF] Decrease alignment of ThunkSection on 64-bit targets from 8 to 4
ThunkSection contains 4-byte instructions on all targets that use
thunks. Thunks should not be used in any performance sensitive places,
and locality/cache line/instruction fetching arguments should not apply.
We use 16 bytes as preferred function alignments for modern PowerPC
cores. In any case, 8 is not optimal.
Differential Revision: https://reviews.llvm.org/D72819
The file was modifiedlld/test/ELF/ppc64-ifunc.s
The file was modifiedlld/test/ELF/aarch64-jump26-thunk.s
The file was modifiedlld/test/ELF/ppc64-dtprel.s
The file was modifiedlld/test/ELF/aarch64-cortex-a53-843419-thunk.s
The file was modifiedlld/test/ELF/aarch64-thunk-pi.s
The file was modifiedlld/test/ELF/ppc64-long-branch.s
The file was modifiedlld/test/ELF/ppc64-toc-restore.s
The file was modifiedlld/ELF/SyntheticSections.cpp
The file was modifiedlld/test/ELF/ppc64-tls-gd.s
The file was modifiedlld/test/ELF/aarch64-thunk-script.s
The file was modifiedlld/test/ELF/aarch64-call26-thunk.s
Commit 8ee2d1689664d4d116c693ff427159396474c30d by kparzysz
[Hexagon] Add a target feature to disable compound instructions
This affects the following instructions: Tag: M4_mpyrr_addr     Syntax:
Ry32 = add(Ru32,mpyi(Ry32,Rs32)) Tag: M4_mpyri_addr_u2  Syntax: Rd32 =
add(Ru32,mpyi(#u6:2,Rs32)) Tag: M4_mpyri_addr     Syntax: Rd32 =
add(Ru32,mpyi(Rs32,#u6)) Tag: M4_mpyri_addi     Syntax: Rd32 =
add(#u6,mpyi(Rs32,#U6)) Tag: M4_mpyrr_addi     Syntax: Rd32 =
add(#u6,mpyi(Rs32,Rt32)) Tag: S4_addaddi        Syntax: Rd32 =
add(Rs32,add(Ru32,#s6)) Tag: S4_subaddi        Syntax: Rd32 =
add(Rs32,sub(#s6,Ru32)) Tag: S4_or_andix       Syntax: Rx32 =
or(Ru32,and(Rx32,#s10)) Tag: S4_andi_asl_ri    Syntax: Rx32 =
and(#u8,asl(Rx32,#U5)) Tag: S4_ori_asl_ri     Syntax: Rx32 =
or(#u8,asl(Rx32,#U5)) Tag: S4_addi_asl_ri    Syntax: Rx32 =
add(#u8,asl(Rx32,#U5)) Tag: S4_subi_asl_ri    Syntax: Rx32 =
sub(#u8,asl(Rx32,#U5)) Tag: S4_andi_lsr_ri    Syntax: Rx32 =
and(#u8,lsr(Rx32,#U5)) Tag: S4_ori_lsr_ri     Syntax: Rx32 =
or(#u8,lsr(Rx32,#U5)) Tag: S4_addi_lsr_ri    Syntax: Rx32 =
add(#u8,lsr(Rx32,#U5)) Tag: S4_subi_lsr_ri    Syntax: Rx32 =
sub(#u8,lsr(Rx32,#U5))
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
The file was modifiedllvm/lib/Target/Hexagon/HexagonSubtarget.h
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonPatterns.td
The file was addedllvm/test/CodeGen/Hexagon/feature-compound.ll
The file was modifiedllvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td
The file was modifiedllvm/lib/Target/Hexagon/Hexagon.td