Changes

Add ARM64 Windows on Arm buildbots

This patch adds 2 new machines:
* linaro-armv8-windows-msvc-01
* linaro-armv8-windows-msvc-02
and 2 new builders:
* clang-arm64-windows-msvc
* clang-arm64-windows-msvc-2stage
to test LLVM on Windows on Arm platform.

The machines are Microsoft Surface X Pro laptops configured for 24x7 workload.

The host build environment is bootstrapped based on LLVM 11 custom build and
uses headers and libraries from MS Visual Studio 2019.  To accommodate the custom
setup we add "manual" value for "vs" parameter to ClangBuilder factory, which allows
to use manually pre-configured MSVC environment instead of initializing it during
build by running old-school vcvarsall.bat.

Finally, the bots have known failures in MCJIT unit-tests, which we are working on.
Once the failures are fixed, we'll enable unit-testsuite in both builders.

Reviewed By: gkistanova, omjavaid

Differential Revision: https://reviews.llvm.org/D87186

ang-x86-ninja removed MSVC environment setup

fixed compiler argument

Otherwise MSVC would have been used...

[Test] Missing range check removal opportunity

[UpdateCCTestChecks] Include generated functions if asked

Add the --include-generated-funcs option to update_cc_test_checks.py so that any
functions created by the compiler that don't exist in the source will also be
checked.

We need to maintain the output order of generated function checks so that
CHECK-LABEL works properly.  To do so, maintain a list of functions output for
each prefix in the order they are output.  Use this list to output checks for
generated functions in the proper order.

Differential Revision: https://reviews.llvm.org/D83004

[DWARFYAML][test] Use 'CHECK-NEXT:' to make checkers stricter. NFC.

This patch makes checkers stricter so that we are able to avoid
some potential problems earlier.

Reviewed By: jhenderson, MaskRay

Differential Revision: https://reviews.llvm.org/D87876

[DWARFYAML] Make the include_directories, file_names and opcodes fields of the line table optional.

This patch makes the include_directories, file_names and opcodes fields
of the line table optional. This helps us simplify some tests.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D87878

[libunwind] Support for leaf function unwinding.

Unwinding leaf function is useful in cases when the backtrace finds a
leaf function for example when it caused a signal.
This patch also add the support for the DW_CFA_undefined because it marks
the end of the frames.

Ryan Prichard provided code for the tests.

Reviewed By: #libunwind, mstorsjo

Differential Revision: https://reviews.llvm.org/D83573

Reland with limit the test to the x86_64-linux target.

[InstSimplify] add another test for NaN propagation; NFC

[AMDGPU] Set DS alignment requirements to be more strict

Alignment requirements for ds_read/write_b96/b128 for gfx9 and onward are
now the same as for other GCN subtargets. This way we can avoid any
unintentional use of these instructions on systems that do not support dword
alignment and instead require natural alignment.
This also makes 'SH_MEM_CONFIG.alignment_mode == STRICT' the default.

Differential Revision: https://reviews.llvm.org/D87821

[SLP] Allow reordering of vectorization trees with reused instructions.

If some leaves have the same instructions to be vectorized, we may
incorrectly evaluate the best order for the root node (it is built for the
vector of instructions without repeated instructions and, thus, has less
elements than the root node). In this case we just can not try to reorder
the tree + we may calculate the wrong number of nodes that requre the
same reordering.
For example, if the root node is \<a+b, a+c, a+d, f+e\>, then the leaves
are \<a, a, a, f\> and \<b, c, d, e\>. When we try to vectorize the first
leaf, it will be shrink to \<a, b\>. If instructions in this leaf should
be reordered, the best order will be \<1, 0\>. We need to extend this
order for the root node. For the root node this order should look like
\<3, 0, 1, 2\>. This patch allows extension of the orders of the nodes
with the reused instructions.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D45263

Revert "[amdgpu] Lower SGPR-to-VGPR copy in the final phase of ISel."

This reverts commit c3492a1aa1b98c8d81b0969d52cea7681f0624c2.

I think this is the wrong strategy and wrong place to do this
transform anyway. Also reverts follow up commit
7d593d0d6905b55ca1124fca5e4d1ebb17203138.

emacs: Add nofree and willreturn to list of attributes

IR: Move denormal mode parsing from MachineFunction to Function

This was just inspecting the IR to begin with, and is useful to check
in some places in the IR.

[InstSimplify] fix fmin/fmax miscompile for partial undef vectors (PR47567)

It would also be correct to return the variable operand in these cases,
but eliminating a variable use is probably better for optimization.

[mlir][StandardToSPIRV] Handle vector of i1 case for lowering zexti to SPIR-V.

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D87887

[clangd] Add option for disabling AddUsing tweak on some namespaces.

For style guides forbid "using" declarations for namespaces like "std".
With this new config option, AddUsing can be selectively disabled on
those.

Differential Revision: https://reviews.llvm.org/D87775

[AIX] Enable large code model when building with clang

[DAG] BuildVectorSDNode::getSplatValue - pull out repeated getNumOperands() calls. NFCI.

[X86][AVX] Add missing i686 broadcastm test coverage

[mlir][openacc] Support Index and AnyInteger in loop op

Following patch D87712, this patch switch AnyInteger for operands gangNum, gangStatic,
workerNum, vectoreLength and tileOperands to Index and AnyInteger.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D87848

[mlir][openacc] Add missing operands for acc.data operation

Add missing operands to represent copyin with readonly modifier, copyout with zero modifier
and create with zero modifier.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D87874

[MLIR][SPIRV] Create new ctx for deserialization in roundtrips.

Roundtripping SPIR-V modules used the same MLIRContext object for both
ways of the trip. This resulted in deserialization using a context
object already containing Types constructed during serialization.
This commit rectifies that by creating a new MLIRContext during
deserialization.

Reviewed By: mravishankar, antiagainst

Differential Revision: https://reviews.llvm.org/D87692

[DFSan] Add strpbrk wrapper.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D87849

[X86][AVX] lowerBuildVectorAsBroadcast - improve i64 BROADCASTM lowering on 32-bit targets

We already handle the the cases where we have a 'zero extended splat' build vector (a, 0, 0, 0, a, 0, 0, 0, ...) but were missing the case where the 'a' scalar was zero-extended as well - such as i64 -> vXi64 splat cases on 32-bit targets.

[MLIR][ODS] Add constBuilderCall for TypeArrayAttr

constBuilderCall was not defined for TypeArrayAttr, resulting in tblgen not emitting the correct code when TypeArrayAttr is used with a default valued attribute.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D87907

Extending Baremetal toolchain's support for the rtlib option.

Differential Revision: https://reviews.llvm.org/D87164

Patch by Manuel Carrasco!

Use one more byte to silence a warning from Vistual C++

[NFC][ScheduleDAG] Remove unused EntrySU SUnit

EntrySU doesn't seem to be used at all when building the ScheduleDAG.

Differential Revision: https://reviews.llvm.org/D87867

[libomptarget] Disable build of amdgpu plugin as it doesn't build with rocm.

[clang-format] Add a option for the position of Java static import

 Some Java style guides and IDEs group Java static imports after
 non-static imports. This patch allows clang-format to control
 the location of static imports.

Patch by: @bc-lee

Reviewed By: MyDeveloperDay, JakeMerdichAMD

Differential Revision: https://reviews.llvm.org/D87201

[clang-format] NFC ensure the clang-format tests remain clang-formatted

[mlir][shape] Extend shape.cstr_require with a message.

I realized when using this that one can't get very good error messages
without an additional message attribute.

Differential Revision: https://reviews.llvm.org/D87875

[clangd] Add Random Forest runtime for code completion.

Summary:
[WIP]
- Proposes a json format for representing Random Forest model.
- Proposes a way to test the generated runtime using a test model.

TODO:
- Add generated source code snippet for easier review.
- Fix unused label warning.
- Figure out required using declarations for CATEGORICAL columns from Features.json.
- Necessary Google3 internal modifications for blaze before landing.
- Add documentation for format of the model.
- Document more.

Subscribers: mgorny, ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D83814

[AArch64][GlobalISel] Make <8 x s8> of G_BUILD_VECTOR legal.

AMDGPU: Don't sometimes allow instructions before lowered si_end_cf

Since 6524a7a2b9ca072bd7f7b4355d1230e70c679d2f, this would sometimes
not emit the or to exec at the beginning of the block, where it really
has to be. If there is an instruction that defines one of the source
operands, split the block and turn the si_end_cf into a terminator.

This avoids regressions when regalloc fast is switched to inserting
reloads at the beginning of the block, instead of spills at the end of
the block.

In a future change, this should always split the block.

[flang] Rework preprocessing of stringification

Hew more closely to the C17 standard; perform macro replacement
of arguments to function-like macros unless they're being stringified
or pasted.  Test with a model "assert" macro idiom that exposed
the problem.

Differential Revision: https://reviews.llvm.org/D87650

[ASan][NewPM] Fix byref-args.ll under NPM

[Sema] Handle objc_super special lookup when checking builtin compatibility

objc_super is special and needs LookupPredefedObjCSuperType() called before performing builtin type comparisons.
This fixes an error when compiling macOS headers. A test is added.

Differential Revision: https://reviews.llvm.org/D87917

DebugInfo: Tidy up initializing multi-section contributions in DWARFContext

[test][HWAsan] Fix kernel-inline.ll under NPM

[CodeGen] emit CG profile for COFF object file

I forgot to add emission of CG profile for COFF object file, when adding the support (https://reviews.llvm.org/D81775)

Differential Revision: https://reviews.llvm.org/D87811

Reapply "RegAllocFast: Record internal state based on register units"

The regressions this caused should be fixed when
https://reviews.llvm.org/D52010 is applied.

This reverts commit a21387c65470417c58021f8d3194a4510bb64f46.

RegAllocFast: Rewrite and improve

This rewrites big parts of the fast register allocator. The basic
strategy of doing block-local allocation hasn't changed but I tweaked
several details:

Track register state on register units instead of physical
registers. This simplifies and speeds up handling of register aliases.
Process basic blocks in reverse order: Definitions are known to end
register livetimes when walking backwards (contrary when walking
forward then uses may or may not be a kill so we need heuristics).

Check register mask operands (calls) instead of conservatively
assuming everything is clobbered.  Enhance heuristics to detect
killing uses: In case of a small number of defs/uses check if they are
all in the same basic block and if so the last one is a killing use.
Enhance heuristic for copy-coalescing through hinting: We check the
first k defs of a register for COPYs rather than relying on there just
being a single definition.  When testing this on the full llvm
test-suite including SPEC externals I measured:

average 5.1% reduction in code size for X86, 4.9% reduction in code on
aarch64. (ranging between 0% and 20% depending on the test) 0.5%
faster compiletime (some analysis suggests the pass is slightly slower
than before, but we more than make up for it because later passes are
faster with the reduced instruction count)

Also adds a few testcases that were broken without this patch, in
particular bug 47278.

Patch mostly by Matthias Braun

CodeGen: Move split block utility to MachineBasicBlock

AMDGPU needs this in several places, so consolidate them here.

[X86][AVX] Add missing non AVX512VL broadcastm test coverage

PR47468: Fix findPHICopyInsertPoint, so that copies aren't incorrectly inserted after an INLINEASM_BR.

findPHICopyInsertPoint special cases placement in a block with a
callbr or invoke in it. In that case, we must ensure that the copy is
placed before the INLINEASM_BR or call instruction, if the register is
defined prior to that instruction, because it may jump out of the
block.

Previously, the code placed it immediately after the last def _or
use_. This is wrong, if the use is the instruction which may jump.  We
could correctly place it immediately after the last def (ignoring
uses), but that is non-optimal for register pressure.

Instead, place the copy after the last def, or before the
call/inlineasm_br, whichever is later.

Differential Revision: https://reviews.llvm.org/D87865

DebugInfo: Simplify line table parsing to take all the units together, rather than CUs and TUs separately

Linewrap & remove some dead typedefs from previous commit

Cleanup for 51a505340dfdfdfd9ab32c7267a74db3cdeefa56

[InstCombine][SVE] Skip scalable type for InstCombiner::getFlippedStrictnessPredicateAndConstant.

We cannot iterate on scalable vector, the number of elements is unknown at compile-time.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D87918

[test][TSan] Fix tests under NPM

Under NPM, the TSan passes are split into a module and function pass. A
couple tests were testing for inserted module constructors, which is
only part of the module pass.

[X86][AVX] lowerBuildVectorAsBroadcast - improve BROADCASTM lowering on non-VLX targets

Broadcast to a ZMM type then extract the low subvector.

scudo: Add an API for disabling memory initialization per-thread.

Here "memory initialization" refers to zero- or pattern-init on
non-MTE hardware, or (where possible to avoid) memory tagging on MTE
hardware. With shared TSD the per-thread memory initialization state
is stored in bit 0 of the TLS slot, similar to PointerIntPair in LLVM.

Differential Revision: https://reviews.llvm.org/D87739

Add ARM64 Windows on Arm buildbots

This patch adds 2 new machines:
* linaro-armv8-windows-msvc-01
* linaro-armv8-windows-msvc-02
and 2 new builders:
* clang-arm64-windows-msvc
* clang-arm64-windows-msvc-2stage
to test LLVM on Windows on Arm platform.

The machines are Microsoft Surface X Pro laptops configured for 24x7 workload.

The host build environment is bootstrapped based on LLVM 11 custom build and
uses headers and libraries from MS Visual Studio 2019.  To accommodate the custom
setup we add "manual" value for "vs" parameter to ClangBuilder factory, which allows
to use manually pre-configured MSVC environment instead of initializing it during
build by running old-school vcvarsall.bat.

Finally, the bots have known failures in MCJIT unit-tests, which we are working on.
Once the failures are fixed, we'll enable unit-testsuite in both builders.

Reviewed By: gkistanova, omjavaid

Differential Revision: https://reviews.llvm.org/D87186

ang-x86-ninja removed MSVC environment setup

fixed compiler argument

Otherwise MSVC would have been used...