Commit
09a3737384ec34c6b216e7c6b9ca768c26ffb1d1
by mkazantsev[Test] Missing range check removal opportunity
|
 | llvm/test/Transforms/IndVarSimplify/checks_against_min_value.ll |
Commit
7c8bb409f31ebbe24ac978e123efcef961a58340
by David A Greene[UpdateCCTestChecks] Include generated functions if asked
Add the --include-generated-funcs option to update_cc_test_checks.py so that any functions created by the compiler that don't exist in the source will also be checked.
We need to maintain the output order of generated function checks so that CHECK-LABEL works properly. To do so, maintain a list of functions output for each prefix in the order they are output. Use this list to output checks for generated functions in the proper order.
Differential Revision: https://reviews.llvm.org/D83004
|
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/x86_generated_funcs.test |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll |
 | llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/generated_funcs.ll.generated.expected |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/riscv_generated_funcs.ll.nogenerated.expected |
 | clang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.generated.expected |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll |
 | llvm/utils/update_cc_test_checks.py |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/mips_generated_funcs.ll.generated.expected |
 | llvm/test/tools/UpdateTestChecks/update_test_checks/generated_funcs.test |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/sparc_generated_funcs.ll.nogenerated.expected |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/msp430_generated_funcs.test |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/lanai_generated_funcs.ll |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/lanai_generated_funcs.ll.generated.expected |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/riscv_generated_funcs.ll.generated.expected |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/riscv_generated_funcs.ll |
 | llvm/utils/UpdateTestChecks/common.py |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/systemz_generated_funcs.test |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll.nogenerated.expected |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll.nogenerated.expected |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/wasm_generated_funcs.ll.nogenerated.expected |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/amdgpu_generated_funcs.test |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/aarch64_generated_funcs.test |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/arm_generated_funcs.test |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/wasm_generated_funcs.test |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/hexagon_generated_funcs.ll.generated.expected |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/lanai_generated_funcs.ll.nogenerated.expected |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/mips_generated_funcs.ll |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/sparc_generated_funcs.ll |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/lanai_generated_funcs.test |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/hexagon_generated_funcs.test |
 | clang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/hexagon_generated_funcs.ll.nogenerated.expected |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.generated.expected |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.nogenerated.expected |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/msp430_generated_funcs.ll.generated.expected |
 | llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/generated_funcs.ll.nogenerated.expected |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/hexagon_generated_funcs.ll |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.generated.expected |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.nogenerated.expected |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/msp430_generated_funcs.ll |
 | llvm/utils/update_test_checks.py |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/sparc_generated_funcs.test |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/sparc_generated_funcs.ll.generated.expected |
 | llvm/utils/update_llc_test_checks.py |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll.nogenerated.expected |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll.generated.expected |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/mips_generated_funcs.ll.nogenerated.expected |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.generated.expected |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/ppc_generated_funcs.test |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/riscv_generated_funcs.test |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.nogenerated.expected |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll.generated.expected |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/wasm_generated_funcs.ll.generated.expected |
 | clang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.no-generated.expected |
 | llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/generated_funcs.ll |
 | llvm/utils/UpdateTestChecks/asm.py |
 | clang/test/utils/update_cc_test_checks/generated-funcs.test |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll.generated.expected |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/msp430_generated_funcs.ll.nogenerated.expected |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/wasm_generated_funcs.ll |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/mips_generated_funcs.test |
Commit
a761e81e2202e6d7ccdf07736942723c95614d7d
by Xing[DWARFYAML][test] Use 'CHECK-NEXT:' to make checkers stricter. NFC.
This patch makes checkers stricter so that we are able to avoid some potential problems earlier.
Reviewed By: jhenderson, MaskRay
Differential Revision: https://reviews.llvm.org/D87876
|
 | llvm/test/ObjectYAML/MachO/DWARF-pubsections.yaml |
 | llvm/test/ObjectYAML/MachO/DWARF-debug_line.yaml |
Commit
2d35092cd2589dffbca1e34a3dc68f6df75818a9
by Xing[DWARFYAML] Make the include_directories, file_names and opcodes fields of the line table optional.
This patch makes the include_directories, file_names and opcodes fields of the line table optional. This helps us simplify some tests.
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D87878
|
 | lldb/unittests/Symbol/Inputs/inlined-functions.yaml |
 | llvm/test/tools/llvm-objcopy/MachO/Inputs/strip-all-with-dwarf.yaml |
 | llvm/test/ObjectYAML/MachO/DWARF5-debug_info.yaml |
 | llvm/test/tools/llvm-dwarfdump/X86/verify_attr_file_indexes.yaml |
 | llvm/test/tools/llvm-gsymutil/ARM_AArch64/fat-macho-dwarf.yaml |
 | llvm/lib/ObjectYAML/DWARFYAML.cpp |
 | llvm/test/tools/llvm-gsymutil/X86/mach-dwarf.yaml |
 | llvm/test/tools/yaml2obj/ELF/DWARF/debug-line.yaml |
 | llvm/test/ObjectYAML/MachO/DWARF-debug_info.yaml |
 | llvm/test/ObjectYAML/MachO/DWARF-debug_line.yaml |
 | llvm/test/tools/llvm-dwarfdump/X86/verify_attr_file_indexes_no_files.yaml |
Commit
22b615a96593f13109a27cabfd1764ec4f558c7a
by daniel.kiss[libunwind] Support for leaf function unwinding.
Unwinding leaf function is useful in cases when the backtrace finds a leaf function for example when it caused a signal. This patch also add the support for the DW_CFA_undefined because it marks the end of the frames.
Ryan Prichard provided code for the tests.
Reviewed By: #libunwind, mstorsjo
Differential Revision: https://reviews.llvm.org/D83573
Reland with limit the test to the x86_64-linux target.
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 | libunwind/test/lit.site.cfg.in |
 | libunwind/src/DwarfInstructions.hpp |
 | libunwind/test/unwind_leaffunction.pass.cpp |
 | libunwind/src/DwarfParser.hpp |
 | libunwind/test/signal_unwind.pass.cpp |
Commit
6690de098e43ac5741297e435aece71b971b5bd2
by spatel[InstSimplify] add another test for NaN propagation; NFC
|
 | llvm/test/Transforms/InstSimplify/ConstProp/cast.ll |
Commit
ae36c02ad0cb0a618c8715404dcfab4cf49c6612
by Mirko.Brkusanin[AMDGPU] Set DS alignment requirements to be more strict
Alignment requirements for ds_read/write_b96/b128 for gfx9 and onward are now the same as for other GCN subtargets. This way we can avoid any unintentional use of these instructions on systems that do not support dword alignment and instead require natural alignment. This also makes 'SH_MEM_CONFIG.alignment_mode == STRICT' the default.
Differential Revision: https://reviews.llvm.org/D87821
|
 | llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll |
 | llvm/test/CodeGen/AMDGPU/ds_write2.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll |
 | llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll |
 | llvm/test/CodeGen/AMDGPU/store-local.96.ll |
 | llvm/test/CodeGen/AMDGPU/load-local.96.ll |
 | llvm/lib/Target/AMDGPU/SIISelLowering.cpp |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir |
 | llvm/test/CodeGen/AMDGPU/load-local.128.ll |
 | llvm/test/CodeGen/AMDGPU/store-local.128.ll |
 | llvm/test/CodeGen/AMDGPU/ds_read2.ll |
 | llvm/test/CodeGen/AMDGPU/store-local.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll |
Commit
455ca0ebb69210046928fedffe292420a30f89ad
by a.bataev[SLP] Allow reordering of vectorization trees with reused instructions.
If some leaves have the same instructions to be vectorized, we may incorrectly evaluate the best order for the root node (it is built for the vector of instructions without repeated instructions and, thus, has less elements than the root node). In this case we just can not try to reorder the tree + we may calculate the wrong number of nodes that requre the same reordering. For example, if the root node is \<a+b, a+c, a+d, f+e\>, then the leaves are \<a, a, a, f\> and \<b, c, d, e\>. When we try to vectorize the first leaf, it will be shrink to \<a, b\>. If instructions in this leaf should be reordered, the best order will be \<1, 0\>. We need to extend this order for the root node. For the root node this order should look like \<3, 0, 1, 2\>. This patch allows extension of the orders of the nodes with the reused instructions.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D45263
|
 | llvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll |
 | llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp |
 | llvm/test/Transforms/SLPVectorizer/X86/vectorize-reorder-reuse.ll |
 | llvm/test/Transforms/SLPVectorizer/X86/jumbled_store_crash.ll |
Commit
27df1652709ba83d6b07f313297e7c796e36dce1
by Matthew.ArsenaultRevert "[amdgpu] Lower SGPR-to-VGPR copy in the final phase of ISel."
This reverts commit c3492a1aa1b98c8d81b0969d52cea7681f0624c2.
I think this is the wrong strategy and wrong place to do this transform anyway. Also reverts follow up commit 7d593d0d6905b55ca1124fca5e4d1ebb17203138.
|
 | llvm/lib/Target/AMDGPU/SIISelLowering.cpp |
 | llvm/test/CodeGen/AMDGPU/sgpr-copy-cse.ll |
 | llvm/test/CodeGen/AMDGPU/wqm.ll |
 | llvm/test/CodeGen/AMDGPU/fabs.ll |
 | llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll |
 | llvm/lib/Target/AMDGPU/SIFoldOperands.cpp |
 | llvm/test/CodeGen/AMDGPU/fneg-fabs.ll |
Commit
05c02eda4552076dc08ce34866b3d8ee33bbf842
by Matthew.Arsenaultemacs: Add nofree and willreturn to list of attributes
|
 | llvm/utils/emacs/llvm-mode.el |
Commit
751a6c5760b8de591cf241effbdad1b1cae67814
by Matthew.ArsenaultIR: Move denormal mode parsing from MachineFunction to Function
This was just inspecting the IR to begin with, and is useful to check in some places in the IR.
|
 | llvm/lib/CodeGen/MachineFunction.cpp |
 | llvm/lib/IR/Function.cpp |
 | llvm/include/llvm/IR/Function.h |
Commit
3f100e64b429b6468e9a2c5b3e7ef7757a06dc48
by spatel[InstSimplify] fix fmin/fmax miscompile for partial undef vectors (PR47567)
It would also be correct to return the variable operand in these cases, but eliminating a variable use is probably better for optimization.
|
 | llvm/lib/Analysis/InstructionSimplify.cpp |
 | llvm/test/Transforms/InstSimplify/fminmax-folds.ll |
Commit
1909b6ac0dbc2f1306103a5ea7f5e59f2232b133
by hanchung[mlir][StandardToSPIRV] Handle vector of i1 case for lowering zexti to SPIR-V.
Reviewed By: mravishankar
Differential Revision: https://reviews.llvm.org/D87887
|
 | mlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp |
 | mlir/test/Conversion/StandardToSPIRV/std-ops-to-spirv.mlir |
Commit
c894bfd1f580e5807fc98cc353b0834e0c5ddc21
by adamcz[clangd] Add option for disabling AddUsing tweak on some namespaces.
For style guides forbid "using" declarations for namespaces like "std". With this new config option, AddUsing can be selectively disabled on those.
Differential Revision: https://reviews.llvm.org/D87775
|
 | clang-tools-extra/clangd/ConfigYAML.cpp |
 | clang-tools-extra/clangd/Config.h |
 | clang-tools-extra/clangd/unittests/TweakTests.cpp |
 | clang-tools-extra/clangd/ConfigFragment.h |
 | clang-tools-extra/clangd/refactor/tweaks/AddUsing.cpp |
 | clang-tools-extra/clangd/ConfigCompile.cpp |
Commit
5d1f8395be94bdf6915ebeb4e51a4290c9497165
by daltenty[AIX] Enable large code model when building with clang
|
 | llvm/cmake/modules/HandleLLVMOptions.cmake |
Commit
d967aaa8fa801e2ed355058db98fd43e4b05edb6
by llvm-dev[DAG] BuildVectorSDNode::getSplatValue - pull out repeated getNumOperands() calls. NFCI.
|
 | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp |
Commit
81dce71acfaccbeea5dfc28c4bc0431952d8d9ca
by llvm-dev[X86][AVX] Add missing i686 broadcastm test coverage
|
 | llvm/test/CodeGen/X86/broadcastm-lowering.ll |
Commit
22dde1f92f68b4249dbae30c119972a17753236a
by clementval[mlir][openacc] Support Index and AnyInteger in loop op
Following patch D87712, this patch switch AnyInteger for operands gangNum, gangStatic, workerNum, vectoreLength and tileOperands to Index and AnyInteger.
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D87848
|
 | mlir/test/Dialect/OpenACC/ops.mlir |
 | mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td |
 | mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp |
Commit
88a1d402d6c60aa182b9d83d39c9e3ab46a830c0
by clementval[mlir][openacc] Add missing operands for acc.data operation
Add missing operands to represent copyin with readonly modifier, copyout with zero modifier and create with zero modifier.
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D87874
|
 | mlir/test/Dialect/OpenACC/ops.mlir |
 | mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp |
 | mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td |
Commit
7b61b192753360427fade9c9c5b68cd76adfc665
by antiagainst[MLIR][SPIRV] Create new ctx for deserialization in roundtrips.
Roundtripping SPIR-V modules used the same MLIRContext object for both ways of the trip. This resulted in deserialization using a context object already containing Types constructed during serialization. This commit rectifies that by creating a new MLIRContext during deserialization.
Reviewed By: mravishankar, antiagainst
Differential Revision: https://reviews.llvm.org/D87692
|
 | mlir/lib/Dialect/SPIRV/Serialization/TranslateRegistration.cpp |
Commit
23bab1eb43d39e7163eb55bcca6e412f68f930e3
by mascasa[DFSan] Add strpbrk wrapper.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D87849
|
 | compiler-rt/lib/dfsan/done_abilist.txt |
 | compiler-rt/test/dfsan/custom.cpp |
 | compiler-rt/lib/dfsan/dfsan_custom.cpp |
Commit
ceadd98c2fd51ab1faa80d142b2a6e080117e5ae
by llvm-dev[X86][AVX] lowerBuildVectorAsBroadcast - improve i64 BROADCASTM lowering on 32-bit targets
We already handle the the cases where we have a 'zero extended splat' build vector (a, 0, 0, 0, a, 0, 0, 0, ...) but were missing the case where the 'a' scalar was zero-extended as well - such as i64 -> vXi64 splat cases on 32-bit targets.
|
 | llvm/test/CodeGen/X86/avx512vlcd-intrinsics-fast-isel.ll |
 | llvm/lib/Target/X86/X86ISelLowering.cpp |
 | llvm/test/CodeGen/X86/avx512cd-intrinsics-fast-isel.ll |
 | llvm/test/CodeGen/X86/broadcastm-lowering.ll |
Commit
3c2e2df8d03e8ac8e7be1733950993090f2b4710
by lyandy[MLIR][ODS] Add constBuilderCall for TypeArrayAttr
constBuilderCall was not defined for TypeArrayAttr, resulting in tblgen not emitting the correct code when TypeArrayAttr is used with a default valued attribute.
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D87907
|
 | mlir/include/mlir/IR/OpBase.td |
 | mlir/test/lib/Dialect/Test/TestOps.td |
Commit
51c5add8547a66caa5fbc9a19a91cd7976944229
by jonathan_roelofsExtending Baremetal toolchain's support for the rtlib option.
Differential Revision: https://reviews.llvm.org/D87164
Patch by Manuel Carrasco!
|
 | clang/lib/Driver/ToolChains/BareMetal.cpp |
 | clang/test/Driver/baremetal.cpp |
Commit
cab6f5b2ab814a4be3fd71aacdbe10298f512833
by jianzhouzhUse one more byte to silence a warning from Vistual C++
|
 | llvm/include/llvm/Bitstream/BitstreamWriter.h |
Commit
0345d88de654259ae90494bf9b015416e2cccacb
by francisvm[NFC][ScheduleDAG] Remove unused EntrySU SUnit
EntrySU doesn't seem to be used at all when building the ScheduleDAG.
Differential Revision: https://reviews.llvm.org/D87867
|
 | llvm/lib/Target/AMDGPU/SIMachineScheduler.h |
 | llvm/lib/CodeGen/MacroFusion.cpp |
 | llvm/include/llvm/CodeGen/MachineScheduler.h |
 | llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp |
 | llvm/lib/CodeGen/ScheduleDAG.cpp |
 | llvm/lib/CodeGen/PostRASchedulerList.cpp |
 | llvm/include/llvm/CodeGen/ScheduleDAG.h |
 | llvm/lib/CodeGen/MachineScheduler.cpp |
 | llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp |
 | llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp |
 | llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp |
 | llvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp |
 | llvm/lib/CodeGen/ScheduleDAGInstrs.cpp |
Commit
a9be2b5cb2b3e752c6de2fab24aa5ad94500802b
by jonchesterfield[libomptarget] Disable build of amdgpu plugin as it doesn't build with rocm.
|
 | openmp/libomptarget/plugins/CMakeLists.txt |
Commit
2e7add812eb7bdd90bd0f0fc3b633515edd55f27
by mydeveloperday[clang-format] Add a option for the position of Java static import
Some Java style guides and IDEs group Java static imports after non-static imports. This patch allows clang-format to control the location of static imports.
Patch by: @bc-lee
Reviewed By: MyDeveloperDay, JakeMerdichAMD
Differential Revision: https://reviews.llvm.org/D87201
|
 | clang/unittests/Format/FormatTest.cpp |
 | clang/lib/Format/Format.cpp |
 | clang/include/clang/Format/Format.h |
 | clang/docs/ClangFormatStyleOptions.rst |
 | clang/unittests/Format/SortImportsTestJava.cpp |
Commit
a16e4a63ae7c1933291577723324e412e087dc8e
by mydeveloperday[clang-format] NFC ensure the clang-format tests remain clang-formatted
|
 | clang/unittests/Format/FormatTestCSharp.cpp |
Commit
7c44651360dd94e17011fd1cd7ec3c755e0363b4
by silvasean[mlir][shape] Extend shape.cstr_require with a message.
I realized when using this that one can't get very good error messages without an additional message attribute.
Differential Revision: https://reviews.llvm.org/D87875
|
 | mlir/include/mlir/Dialect/Shape/IR/ShapeOps.td |
 | mlir/test/Dialect/Shape/canonicalize.mlir |
 | mlir/test/Dialect/Shape/ops.mlir |
Commit
9b6765e784b39c88cb8cdb85ab083e6c95a997ed
by usx[clangd] Add Random Forest runtime for code completion.
Summary: [WIP] - Proposes a json format for representing Random Forest model. - Proposes a way to test the generated runtime using a test model.
TODO: - Add generated source code snippet for easier review. - Fix unused label warning. - Figure out required using declarations for CATEGORICAL columns from Features.json. - Necessary Google3 internal modifications for blaze before landing. - Add documentation for format of the model. - Document more.
Subscribers: mgorny, ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D83814
|
 | clang-tools-extra/clangd/unittests/CodeCompleteTests.cpp |
 | clang-tools-extra/clangd/quality/README.md |
 | clang-tools-extra/clangd/CMakeLists.txt |
 | clang-tools-extra/clangd/quality/CompletionModelCodegen.py |
 | clang-tools-extra/clangd/unittests/decision_forest_model/features.json |
 | clang-tools-extra/clangd/quality/CompletionModel.cmake |
 | clang-tools-extra/clangd/unittests/decision_forest_model/CategoricalFeature.h |
 | clang-tools-extra/clangd/unittests/DecisionForestTests.cpp |
 | clang-tools-extra/clangd/unittests/CMakeLists.txt |
 | clang-tools-extra/clangd/quality/model/forest.json |
 | clang-tools-extra/clangd/quality/model/features.json |
 | clang-tools-extra/clangd/unittests/decision_forest_model/forest.json |
Commit
615695de27e417d6b444cd983e6f636373afc8c9
by Amara Emerson[AArch64][GlobalISel] Make <8 x s8> of G_BUILD_VECTOR legal.
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 | llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir |
 | llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp |
Commit
0576f436e577cede25810729aef236ec8c649446
by Matthew.ArsenaultAMDGPU: Don't sometimes allow instructions before lowered si_end_cf
Since 6524a7a2b9ca072bd7f7b4355d1230e70c679d2f, this would sometimes not emit the or to exec at the beginning of the block, where it really has to be. If there is an instruction that defines one of the source operands, split the block and turn the si_end_cf into a terminator.
This avoids regressions when regalloc fast is switched to inserting reloads at the beginning of the block, instead of spills at the end of the block.
In a future change, this should always split the block.
|
 | llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir |
 | llvm/lib/Target/AMDGPU/SIInstructions.td |
 | llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp |
 | llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp |
 | llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir |
 | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp |
Commit
01def7f7c3f1f762ce57a89aceb85214669911c3
by pklausler[flang] Rework preprocessing of stringification
Hew more closely to the C17 standard; perform macro replacement of arguments to function-like macros unless they're being stringified or pasted. Test with a model "assert" macro idiom that exposed the problem.
Differential Revision: https://reviews.llvm.org/D87650
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 | flang/lib/Parser/preprocessor.cpp |
 | flang/lib/Parser/prescan.h |
 | flang/test/Preprocessing/assert.F90 |
 | flang/lib/Parser/preprocessor.h |
 | flang/lib/Parser/parsing.cpp |
 | flang/lib/Parser/prescan.cpp |
Commit
06fe76cc4f5972b04dd4ad7b9dcb4425a73dccba
by aeubanks[ASan][NewPM] Fix byref-args.ll under NPM
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 | llvm/test/Instrumentation/AddressSanitizer/byref-args.ll |
Commit
a1aa330b202f97ecd243ea9ef0c7ac00a80ea653
by raul.tambre[Sema] Handle objc_super special lookup when checking builtin compatibility
objc_super is special and needs LookupPredefedObjCSuperType() called before performing builtin type comparisons. This fixes an error when compiling macOS headers. A test is added.
Differential Revision: https://reviews.llvm.org/D87917
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 | clang/lib/Sema/SemaDecl.cpp |
 | clang/test/SemaObjCXX/builtin-objcsuper.mm |
Commit
e0802fe0162fcab12de5f134dc0848a8e4dfbc92
by dblaikieDebugInfo: Tidy up initializing multi-section contributions in DWARFContext
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 | llvm/lib/DebugInfo/DWARF/DWARFContext.cpp |
Commit
d419e34c4d7e9e0b2b3f99b77246e57a03b2459b
by aeubanks[test][HWAsan] Fix kernel-inline.ll under NPM
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 | llvm/test/Instrumentation/HWAddressSanitizer/kernel-inline.ll |
Commit
91aed9bf975f1e4346cc8f4bdefc98436386ced2
by zequanwu[CodeGen] emit CG profile for COFF object file
I forgot to add emission of CG profile for COFF object file, when adding the support (https://reviews.llvm.org/D81775)
Differential Revision: https://reviews.llvm.org/D87811
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 | llvm/test/MC/COFF/cgprofile.ll |
 | llvm/include/llvm/Target/TargetLoweringObjectFile.h |
 | llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp |
 | llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h |
 | llvm/lib/Target/TargetLoweringObjectFile.cpp |
Commit
870fd53e4f6357946f4bad0b861c510cd107420c
by Matthew.ArsenaultReapply "RegAllocFast: Record internal state based on register units"
The regressions this caused should be fixed when https://reviews.llvm.org/D52010 is applied.
This reverts commit a21387c65470417c58021f8d3194a4510bb64f46.
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 | llvm/test/CodeGen/X86/atomic-unordered.ll |
 | llvm/test/CodeGen/X86/pr39733.ll |
 | llvm/test/CodeGen/X86/pr30430.ll |
 | llvm/test/CodeGen/X86/2009-04-14-IllegalRegs.ll |
 | llvm/test/CodeGen/X86/lvi-hardening-loads.ll |
 | llvm/test/CodeGen/AMDGPU/spill-m0.ll |
 | llvm/test/CodeGen/AArch64/popcount.ll |
 | llvm/test/CodeGen/X86/crash-O0.ll |
 | llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll |
 | llvm/test/CodeGen/AArch64/fast-isel-sp-adjust.ll |
 | llvm/test/CodeGen/X86/avx-load-store.ll |
 | llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll |
 | llvm/lib/CodeGen/RegAllocFast.cpp |
 | llvm/test/CodeGen/X86/pr32345.ll |
 | llvm/test/CodeGen/X86/mixed-ptr-sizes.ll |
 | llvm/test/CodeGen/Mips/atomic-min-max.ll |
 | llvm/test/CodeGen/X86/pr1489.ll |
 | llvm/test/CodeGen/X86/pr27591.ll |
 | llvm/test/CodeGen/X86/pr32340.ll |
 | llvm/test/CodeGen/X86/swifterror.ll |
 | llvm/test/CodeGen/X86/pr47000.ll |
 | llvm/test/CodeGen/X86/extend-set-cc-uses-dbg.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll |
 | llvm/test/CodeGen/X86/pr32241.ll |
 | llvm/test/CodeGen/X86/regalloc-fast-missing-live-out-spill.mir |
 | llvm/test/CodeGen/X86/swift-return.ll |
 | llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll |
 | llvm/test/CodeGen/ARM/legalize-bitcast.ll |
 | llvm/test/CodeGen/Mips/atomic.ll |
 | llvm/test/CodeGen/PowerPC/vsx.ll |
 | llvm/test/CodeGen/AMDGPU/wwm-reserved.ll |
 | llvm/test/CodeGen/X86/atomic64.ll |
 | llvm/test/CodeGen/X86/fast-isel-nontemporal.ll |
 | llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll |
 | llvm/test/DebugInfo/X86/op_deref.ll |
 | llvm/test/CodeGen/X86/pr32284.ll |
 | llvm/test/CodeGen/X86/pr34592.ll |
 | llvm/test/CodeGen/PowerPC/addegluecrash.ll |
 | llvm/test/CodeGen/X86/pr30813.ll |
 | llvm/test/CodeGen/SPARC/fp16-promote.ll |
 | llvm/test/CodeGen/X86/atomic32.ll |
 | llvm/test/CodeGen/Mips/implicit-sret.ll |
 | llvm/test/CodeGen/X86/avx512-mask-zext-bugfix.ll |
 | llvm/test/CodeGen/X86/pr32451.ll |
 | llvm/test/CodeGen/X86/pr44749.ll |
 | llvm/test/CodeGen/PowerPC/popcount.ll |
 | llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll |
Commit
c8757ff3aa7dd7a25a6343f6ef74a70c7be04325
by Matthew.ArsenaultRegAllocFast: Rewrite and improve
This rewrites big parts of the fast register allocator. The basic strategy of doing block-local allocation hasn't changed but I tweaked several details:
Track register state on register units instead of physical registers. This simplifies and speeds up handling of register aliases. Process basic blocks in reverse order: Definitions are known to end register livetimes when walking backwards (contrary when walking forward then uses may or may not be a kill so we need heuristics).
Check register mask operands (calls) instead of conservatively assuming everything is clobbered. Enhance heuristics to detect killing uses: In case of a small number of defs/uses check if they are all in the same basic block and if so the last one is a killing use. Enhance heuristic for copy-coalescing through hinting: We check the first k defs of a register for COPYs rather than relying on there just being a single definition. When testing this on the full llvm test-suite including SPEC externals I measured:
average 5.1% reduction in code size for X86, 4.9% reduction in code on aarch64. (ranging between 0% and 20% depending on the test) 0.5% faster compiletime (some analysis suggests the pass is slightly slower than before, but we more than make up for it because later passes are faster with the reduced instruction count)
Also adds a few testcases that were broken without this patch, in particular bug 47278.
Patch mostly by Matthias Braun
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 | llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm.ll |
 | llvm/test/CodeGen/X86/bug47278.mir |
 | llvm/test/CodeGen/X86/pr47000.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zext_and_sext.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_split_because_of_memsize_or_align.ll |
 | llvm/test/CodeGen/PowerPC/aix-overflow-toc.py |
 | llvm/test/CodeGen/AArch64/swifterror.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ctlz.ll |
 | llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll |
 | llvm/test/CodeGen/X86/pr11415.ll |
 | llvm/test/CodeGen/ARM/ldrd.ll |
 | llvm/test/CodeGen/PowerPC/anon_aggr.ll |
 | llvm/test/CodeGen/X86/pr32451.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll |
 | llvm/test/CodeGen/X86/atomic64.ll |
 | llvm/test/CodeGen/Hexagon/vect/vect-load-v4i16.ll |
 | llvm/test/CodeGen/Mips/Fast-ISel/memtest1.ll |
 | llvm/test/CodeGen/PowerPC/elf-common.ll |
 | llvm/test/CodeGen/Mips/micromips-eva.mir |
 | llvm/test/DebugInfo/X86/parameters.ll |
 | llvm/test/CodeGen/AMDGPU/unexpected-reg-unit-state.mir |
 | llvm/test/DebugInfo/X86/spill-indirect-nrvo.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address_pic.ll |
 | llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll |
 | llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll |
 | llvm/test/CodeGen/AArch64/arm64_32-null.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub_vec.ll |
 | llvm/test/CodeGen/X86/win64_eh.ll |
 | llvm/test/CodeGen/AMDGPU/wwm-reserved.ll |
 | llvm/test/DebugInfo/AArch64/prologue_end.ll |
 | llvm/test/CodeGen/X86/pr32241.ll |
 | llvm/test/CodeGen/PowerPC/addegluecrash.ll |
 | llvm/test/CodeGen/AMDGPU/fast-ra-kills-vcc.mir |
 | llvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir |
 | llvm/test/CodeGen/Mips/msa/ldr_str.ll |
 | llvm/test/DebugInfo/X86/prologue-stack.ll |
 | llvm/test/CodeGen/ARM/swifterror.ll |
 | llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll |
 | llvm/test/CodeGen/ARM/fast-isel-call.ll |
 | llvm/test/DebugInfo/Mips/prologue_end.ll |
 | llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll |
 | llvm/test/CodeGen/AMDGPU/reserve-vgpr-for-sgpr-spill.ll |
 | llvm/test/DebugInfo/X86/reference-argument.ll |
 | llvm/test/CodeGen/Mips/copy-fp64.ll |
 | llvm/test/CodeGen/X86/2013-10-14-FastISel-incorrect-vreg.ll |
 | llvm/test/CodeGen/X86/fast-isel-select-sse.ll |
 | llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fcmp.ll |
 | llvm/test/CodeGen/X86/pr34592.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/aggregate_struct_return.ll |
 | llvm/test/CodeGen/AArch64/unwind-preserved.ll |
 | llvm/test/CodeGen/ARM/stack-guard-reassign.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ctpop.ll |
 | llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/branch.ll |
 | llvm/test/CodeGen/ARM/Windows/alloca.ll |
 | llvm/test/CodeGen/X86/pr1489.ll |
 | llvm/test/DebugInfo/X86/sret.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/float_constants.ll |
 | llvm/test/CodeGen/X86/x86-32-intrcc.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll |
 | llvm/test/CodeGen/PowerPC/vsx.ll |
 | llvm/test/CodeGen/AMDGPU/fastregalloc-illegal-subreg-physreg.mir |
 | llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll |
 | llvm/test/CodeGen/X86/avx-load-store.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/store_4_unaligned.ll |
 | llvm/test/CodeGen/X86/phys-reg-local-regalloc.ll |
 | llvm/test/CodeGen/X86/x86-64-intrcc.ll |
 | llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll |
 | llvm/test/CodeGen/AMDGPU/spill-agpr.mir |
 | llvm/test/CodeGen/X86/atomic-monotonic.ll |
 | llvm/test/DebugInfo/AArch64/frameindices.ll |
 | llvm/test/CodeGen/AMDGPU/spill192.mir |
 | llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/test_TypeInfoforMF.ll |
 | llvm/test/DebugInfo/X86/pieces-1.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll |
 | llvm/test/CodeGen/ARM/legalize-bitcast.ll |
 | llvm/lib/CodeGen/RegAllocFast.cpp |
 | llvm/test/CodeGen/X86/fast-isel-cmp-branch.ll |
 | llvm/test/CodeGen/X86/fast-isel-select.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec.ll |
 | llvm/test/DebugInfo/ARM/prologue_end.ll |
 | llvm/test/CodeGen/X86/crash-O0.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll |
 | llvm/test/DebugInfo/X86/op_deref.ll |
 | llvm/test/CodeGen/X86/pr42452.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/call.ll |
 | llvm/test/CodeGen/X86/pr27591.ll |
 | llvm/test/CodeGen/AArch64/GlobalISel/darwin-tls-call-clobber.ll |
 | llvm/test/CodeGen/Mips/Fast-ISel/pr40325.ll |
 | llvm/test/CodeGen/ARM/debug-info-blocks.ll |
 | llvm/test/CodeGen/X86/atomic-unordered.ll |
 | llvm/test/CodeGen/Mips/implicit-sret.ll |
 | llvm/test/CodeGen/SPARC/fp16-promote.ll |
 | llvm/test/CodeGen/PowerPC/spill-nor0.ll |
 | llvm/test/CodeGen/X86/regalloc-fast-missing-live-out-spill.mir |
 | llvm/test/CodeGen/X86/extend-set-cc-uses-dbg.ll |
 | llvm/test/CodeGen/ARM/thumb-big-stack.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll |
 | llvm/test/CodeGen/AArch64/combine-loads.ll |
 | llvm/test/CodeGen/PowerPC/stack-guard-reassign.ll |
 | llvm/test/DebugInfo/Mips/delay-slot.ll |
 | llvm/test/CodeGen/X86/pr32284.ll |
 | llvm/test/CodeGen/AMDGPU/spill-m0.ll |
 | llvm/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll |
 | llvm/test/DebugInfo/X86/subreg.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/store_split_because_of_memsize_or_align.ll |
 | llvm/test/DebugInfo/X86/fission-ranges.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul_vec.ll |
 | llvm/test/CodeGen/PowerPC/popcount.ll |
 | llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll |
 | llvm/test/CodeGen/Mips/atomic.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/cttz.ll |
 | llvm/test/CodeGen/PowerPC/vsx-args.ll |
 | llvm/test/CodeGen/X86/pr32345.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/var_arg.ll |
 | llvm/test/CodeGen/SystemZ/swifterror.ll |
 | llvm/test/CodeGen/X86/pr39733.ll |
 | llvm/test/CodeGen/X86/pr30430.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s32.ll |
 | llvm/test/CodeGen/X86/fast-isel-x86-64.ll |
 | llvm/test/CodeGen/X86/pr30813.ll |
 | llvm/test/CodeGen/PowerPC/spill-nor0.mir |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bswap.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll |
 | llvm/test/CodeGen/AArch64/arm64_32-fastisel.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll |
 | llvm/test/CodeGen/X86/atomic32.ll |
 | llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll |
 | llvm/test/CodeGen/ARM/cmpxchg-O0-be.ll |
 | llvm/test/CodeGen/AArch64/cmpxchg-O0.ll |
 | llvm/test/CodeGen/ARM/fast-isel-vararg.ll |
 | llvm/test/CodeGen/X86/2009-04-14-IllegalRegs.ll |
 | llvm/test/CodeGen/X86/pr44749.ll |
 | llvm/test/CodeGen/AArch64/popcount.ll |
 | llvm/test/CodeGen/AArch64/swift-return.ll |
 | llvm/test/DebugInfo/X86/dbg-declare-arg.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address.ll |
 | llvm/test/CodeGen/ARM/2010-08-04-StackVariable.ll |
 | llvm/test/CodeGen/PowerPC/fp64-to-int16.ll |
 | llvm/test/CodeGen/X86/volatile.ll |
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 | llvm/test/CodeGen/X86/pr34653.ll |
 | llvm/test/CodeGen/X86/stack-protector-msvc.ll |
 | llvm/test/CodeGen/Mips/atomicCmpSwapPW.ll |
 | llvm/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll |
 | llvm/test/CodeGen/X86/stack-protector-strong-macho-win32-xor.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll |
 | llvm/test/CodeGen/X86/swift-return.ll |
 | llvm/test/CodeGen/AArch64/br-cond-not-merge.ll |
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 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s64.ll |
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 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll |
 | llvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll |
 | llvm/test/CodeGen/Mips/atomic64.ll |
 | llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll |
 | llvm/test/CodeGen/ARM/fast-isel-select.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll |
 | llvm/test/CodeGen/ARM/cmpxchg-O0.ll |
 | llvm/test/CodeGen/AArch64/unwind-preserved-from-mir.mir |
 | llvm/test/CodeGen/ARM/crash-greedy-v6.ll |
 | llvm/test/CodeGen/X86/swifterror.ll |
 | llvm/test/CodeGen/AArch64/arm64-fast-isel-br.ll |
 | llvm/test/CodeGen/Mips/atomic-min-max.ll |
 | llvm/test/CodeGen/AArch64/fast-isel-cmpxchg.ll |
 | llvm/test/CodeGen/X86/pr32484.ll |
 | llvm/test/CodeGen/X86/fast-isel-nontemporal.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_4_unaligned.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/brindirect.ll |
 | llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll |
 | llvm/test/CodeGen/PowerPC/fast-isel-pcrel.ll |
 | llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll |
 | llvm/test/CodeGen/X86/avx512-mask-zext-bugfix.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll |
 | llvm/test/CodeGen/X86/atomic6432.ll |
 | llvm/test/CodeGen/SystemZ/swift-return.ll |
 | llvm/test/CodeGen/Thumb2/mve-vector-spill.ll |
Commit
3105d0f84bfa6b765bb88cbf090f557e588764ea
by Matthew.ArsenaultCodeGen: Move split block utility to MachineBasicBlock
AMDGPU needs this in several places, so consolidate them here.
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 | llvm/include/llvm/CodeGen/MachineBasicBlock.h |
 | llvm/lib/CodeGen/MachineBasicBlock.cpp |
 | llvm/lib/Target/AMDGPU/SIISelLowering.cpp |
 | llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp |
Commit
ecba9d793e205ac857196abbd00cd67777e6f51a
by llvm-dev[X86][AVX] Add missing non AVX512VL broadcastm test coverage
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 | llvm/test/CodeGen/X86/broadcastm-lowering.ll |
Commit
f7a53d82c0902147909f28a9295a9d00b4b27d38
by jyknightPR47468: Fix findPHICopyInsertPoint, so that copies aren't incorrectly inserted after an INLINEASM_BR.
findPHICopyInsertPoint special cases placement in a block with a callbr or invoke in it. In that case, we must ensure that the copy is placed before the INLINEASM_BR or call instruction, if the register is defined prior to that instruction, because it may jump out of the block.
Previously, the code placed it immediately after the last def _or use_. This is wrong, if the use is the instruction which may jump. We could correctly place it immediately after the last def (ignoring uses), but that is non-optimal for register pressure.
Instead, place the copy after the last def, or before the call/inlineasm_br, whichever is later.
Differential Revision: https://reviews.llvm.org/D87865
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 | llvm/test/CodeGen/X86/callbr-asm-phi-placement.ll |
 | llvm/lib/CodeGen/PHIEliminationUtils.cpp |
Commit
51a505340dfdfdfd9ab32c7267a74db3cdeefa56
by dblaikieDebugInfo: Simplify line table parsing to take all the units together, rather than CUs and TUs separately
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 | llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp |
 | llvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp |
 | llvm/lib/DebugInfo/DWARF/DWARFContext.cpp |
 | llvm/include/llvm/DebugInfo/DWARF/DWARFDebugLine.h |
Commit
82af17cde8caa8d2d020237f644d4302fc4fa589
by dblaikieLinewrap & remove some dead typedefs from previous commit
Cleanup for 51a505340dfdfdfd9ab32c7267a74db3cdeefa56
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 | llvm/include/llvm/DebugInfo/DWARF/DWARFDebugLine.h |
Commit
9ad6049736c58cca098b13ed128e7de0940f94a0
by huihuiz[InstCombine][SVE] Skip scalable type for InstCombiner::getFlippedStrictnessPredicateAndConstant.
We cannot iterate on scalable vector, the number of elements is unknown at compile-time.
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D87918
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 | llvm/test/Transforms/InstCombine/vscale_cmp.ll |
 | llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp |
Commit
2b1cb6d54a3298204e01a2982e3d00a1f08743a2
by aeubanks[test][TSan] Fix tests under NPM
Under NPM, the TSan passes are split into a module and function pass. A couple tests were testing for inserted module constructors, which is only part of the module pass.
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 | llvm/test/Instrumentation/ThreadSanitizer/tsan_basic.ll |
 | llvm/test/Instrumentation/ThreadSanitizer/do-not-instrument-memory-access.ll |
Commit
4ebd30722af5175282b99938d163ad4459aa5968
by llvm-dev[X86][AVX] lowerBuildVectorAsBroadcast - improve BROADCASTM lowering on non-VLX targets
Broadcast to a ZMM type then extract the low subvector.
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 | llvm/lib/Target/X86/X86ISelLowering.cpp |
 | llvm/test/CodeGen/X86/broadcastm-lowering.ll |
Commit
7bd75b630144ec639dbbf7bcb2797f48380b953b
by peterscudo: Add an API for disabling memory initialization per-thread.
Here "memory initialization" refers to zero- or pattern-init on non-MTE hardware, or (where possible to avoid) memory tagging on MTE hardware. With shared TSD the per-thread memory initialization state is stored in bit 0 of the TLS slot, similar to PointerIntPair in LLVM.
Differential Revision: https://reviews.llvm.org/D87739
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 | compiler-rt/lib/scudo/standalone/include/scudo/interface.h |
 | compiler-rt/lib/scudo/standalone/tests/chunk_test.cpp |
 | compiler-rt/lib/scudo/standalone/chunk.h |
 | compiler-rt/lib/scudo/standalone/combined.h |
 | compiler-rt/lib/scudo/standalone/tests/combined_test.cpp |
 | compiler-rt/lib/scudo/standalone/tsd_exclusive.h |
 | compiler-rt/lib/scudo/standalone/tsd_shared.h |
 | compiler-rt/lib/scudo/standalone/wrappers_c.inc |
 | compiler-rt/lib/scudo/standalone/common.h |