Commit
f1746be66673bc2b59f7aaad1c6a7938ed98194b
by nemanja.i.ibm[Sanitizers] Fix test case that doesn't clean up after itself
Commit https://reviews.llvm.org/rG144e57fc9535 added this test case that creates message queues but does not remove them. The message queues subsequently build up on the machine until the system wide limit is reached. This has caused failures for a number of bots running on a couple of big PPC machines.
This patch just adds the missing cleanup.
|
 | compiler-rt/test/sanitizer_common/TestCases/Linux/sysmsg.c |
Commit
cabe31f415054b45b4fa6c17e4ddf09cc39bf4e8
by i[sanitizers] Remove the message queue with IPC_RMID after D82897
|
 | compiler-rt/test/sanitizer_common/TestCases/Linux/sysmsg.c |
Commit
dfd295431a50aa8bccc0b89da9acf3c48b3d4b29
by Vitaly Buka[RISCV][ASAN] updated platform macros to simplify detection of RISCV64 platform
[2/11] patch series to port ASAN for riscv64
Depends On D87997
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D87998
|
 | compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp |
 | compiler-rt/lib/sanitizer_common/sanitizer_platform.h |
 | compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h |
Commit
47e6851423fd32f0685a643236ad946e23ab14ff
by Jan Korous[Analyzer][WebKit] Use tri-state types for relevant predicates
Some of the predicates can't always be decided - for example when a type definition isn't available. At the same time it's necessary to let client code decide what to do about such cases - specifically we can't just use true or false values as there are callees with conflicting strategies how to handle this.
This is a speculative fix for PR47276.
Differential Revision: https://reviews.llvm.org/D88133
|
 | clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp |
 | clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h |
 | clang/lib/StaticAnalyzer/Checkers/WebKit/NoUncountedMembersChecker.cpp |
 | clang/lib/StaticAnalyzer/Checkers/WebKit/RefCntblBaseVirtualDtorChecker.cpp |
 | clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLambdaCapturesChecker.cpp |
 | clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp |
 | clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLocalVarsChecker.cpp |
 | clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedCallArgsChecker.cpp |
Commit
6c22d00d7896bd7aaad567aa98016c26e78d8dcf
by Vitaly Buka[RISCV][ASAN] implementation of internal syscalls wrappers for riscv64
implements glibc-like wrappers over Linux syscalls.
[3/11] patch series to port ASAN for riscv64
Depends On D87998
Reviewed By: eugenis
Differential Revision: https://reviews.llvm.org/D87572
|
 | compiler-rt/lib/sanitizer_common/CMakeLists.txt |
 | compiler-rt/lib/sanitizer_common/sanitizer_syscall_linux_riscv64.inc |
Commit
96034cb3d1d6d0e4ebe6848ef93707943aeca5dc
by Vitaly Buka[RISCV][ASAN] implementation of clone interceptor for riscv64
[4/11] patch series to port ASAN for riscv64
Depends On D87572
Reviewed By: eugenis, vitalybuka
Differential Revision: https://reviews.llvm.org/D87573
|
 | compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp |
 | compiler-rt/lib/sanitizer_common/sanitizer_linux.h |
Commit
aa1b1d35cbf60f63c7830e6711bf849902975943
by Vitaly Buka[RISCV][ASAN] implementation for vfork interceptor for riscv64
[5/11] patch series to port ASAN for riscv64
Depends On D87573
Reviewed By: eugenis
Differential Revision: https://reviews.llvm.org/D87574
|
 | compiler-rt/lib/asan/asan_interceptors.h |
 | compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors_vfork_riscv64.inc.S |
 | compiler-rt/lib/asan/asan_interceptors_vfork.S |
 | compiler-rt/lib/hwasan/hwasan_interceptors_vfork.S |
Commit
00f6ebef6e347e0d24a8f940fe43656719e88cb8
by Vitaly Buka[RISCV][ASAN] implementation of ThreadSelf for riscv64
[6/11] patch series to port ASAN for riscv64
Depends On D87574
Reviewed By: eugenis
Differential Revision: https://reviews.llvm.org/D87575
|
 | compiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp |
Commit
fe3c1195cfd027fdd28b6d373b3cd9519d5253ec
by joker.ephAdd a dump() method on the pass manager for debugging purpose (NFC)
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D88008
|
 | mlir/lib/Pass/Pass.cpp |
 | mlir/include/mlir/Pass/Pass.h |
 | mlir/include/mlir/Pass/PassManager.h |
Commit
f69e090d7dca6bf2786145a9e97b0a7ddb3b514a
by martin[MC] [Win64EH] Try to generate packed unwind info where possible
In practice, this only gives modest savings (for a 6.5 MB DLL with 230 KB xdata, the xdata sections shrinks by around 2.5 KB); to gain more, the frame lowering would need to be tweaked to more often generate frame layouts that match the canonical layouts that can be written in packed form.
Differential Revision: https://reviews.llvm.org/D87371
|
 | llvm/lib/MC/MCWin64EH.cpp |
 | llvm/test/MC/AArch64/seh-packed-unwind.s |
 | llvm/include/llvm/MC/MCWinEH.h |
Commit
2c4c659666b400b0502e8504a708e050d0a03d6c
by martin[InstCombine] Add parentheses in assert to silence GCC warning. NFC.
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 | llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp |
Commit
b90132399aa994ac6405d0d6437735043bff9314
by martin[CVP] Remove a redundant trailing semicolon, fixing GCC warnings. NFC.
|
 | llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp |
Commit
d7eb917a7cb793f49e16841fc24826b988dd5c8f
by albionapc[PowerPC] Implementation of 128-bit Binary Vector Mod and Sign Extend builtins
This patch implements 128-bit Binary Vector Mod and Sign Extend builtins for PowerPC10.
Differential: https://reviews.llvm.org/D87394#inline-815858
|
 | llvm/include/llvm/IR/IntrinsicsPowerPC.td |
 | llvm/lib/Target/PowerPC/PPCISelLowering.cpp |
 | llvm/test/CodeGen/PowerPC/p10-vector-modulo.ll |
 | clang/test/CodeGen/builtins-ppc-p9vector.c |
 | clang/test/CodeGen/builtins-ppc-p10vector.c |
 | clang/include/clang/Basic/BuiltinsPPC.def |
 | llvm/lib/Target/PowerPC/PPCInstrPrefix.td |
 | clang/lib/Headers/altivec.h |
 | llvm/test/CodeGen/PowerPC/p9-vector-sign-extend.ll |
 | llvm/lib/Target/PowerPC/PPCInstrAltivec.td |
 | llvm/test/CodeGen/PowerPC/p10-vector-sign-extend.ll |
Commit
1fbb5969424493344f1159d53bda5a640e3b27ae
by Vitaly BukaRevert "[RISCV][ASAN] implementation of ThreadSelf for riscv64"
Merged two unrelated commits
This reverts commit 00f6ebef6e347e0d24a8f940fe43656719e88cb8.
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 | compiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp |
Commit
d721a2bc335ad01ff6b3838bc4759cfc35b6c8fa
by Vitaly Buka[NFC] Reformat preprocessor directives
|
 | compiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp |
Commit
809a42e3d53518b824aad28882f9f9397f25b5b3
by Vitaly Buka[RISCV][ASAN] implementation of ThreadSelf for riscv64
[6/11] patch series to port ASAN for riscv64
Depends On D87574
Reviewed By: eugenis
Differential Revision: https://reviews.llvm.org/D87575
|
 | compiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp |
Commit
b62f9f4407a5ed6e5722e177e906efcebebce9eb
by ravishankarm[mlir][Linalg] Add pattern to fold linalg.tensor_reshape that add unit extent dims.
A sequence of two reshapes such that one of them is just adding unit extent dims can be folded to a single reshape.
Differential Revision: https://reviews.llvm.org/D88057
|
 | mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp |
 | mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp |
 | mlir/test/Dialect/Linalg/drop-unit-extent-dims.mlir |
Commit
8d7fd73c3a8ce069cfe48dfcf949b4a59c05c673
by Piotr Sobczak[AMDGPU] Fix merging m0 inits
Fix incorrect merges of m0 inits in loops.
It was assumed that if a clobbering instruction appears in the same block as an init and the clobbering instruction does not dominate the init then it does not interfere with init.
This does not work in the presence of loops, where in this scenario, the clobbering instruction does interfere with the init in another iteration.
To fix this, do not check for block equality and defer the decision to the predecessor check.
Differential Revision: https://reviews.llvm.org/D87882
|
 | llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp |
 | llvm/test/CodeGen/AMDGPU/merge-m0.mir |
Commit
59c4d5aad060927fa95b917c11aad4e310849a4b
by david.sherwood[SVE] Fix InstCombinerImpl::PromoteCastOfAllocation for scalable vectors
In this patch I've fixed some warnings that arose from the implicit cast of TypeSize -> uint64_t. I tried writing a variety of different cases to show how this optimisation might work for scalable vectors and found:
1. The optimisation does not work for cases where the cast type is scalable and the allocated type is not. This because we need to know how many times the cast type fits into the allocated type. 2. If we pass all the various checks for the case when the allocated type is scalable and the cast type is not, then when creating the new alloca we have to take vscale into account. This leads to sub-optimal IR that is worse than the original IR. 3. For the remaining case when both the alloca and cast types are scalable it is hard to find examples where the optimisation would kick in, except for simple bitcasts, because we typically fail the ABI alignment checks.
For now I've changed the code to bail out if only one of the alloca and cast types is scalable. This means we continue to support the existing cases where both types are fixed, and also the specific case when both types are scalable with the same size and alignment, for example a simple bitcast of an alloca to another type.
I've added tests that show we don't attempt to promote the alloca, except for simple bitcasts:
Transforms/InstCombine/AArch64/sve-cast-of-alloc.ll
Differential revision: https://reviews.llvm.org/D87378
|
 | llvm/test/Transforms/InstCombine/AArch64/sve-cast-of-alloc.ll |
 | llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp |
Commit
e46c1def523323eedfad1174fd2fabbece8f40cc
by Raphael IsemannRevert "[libc++] Implement LWG1203"
This reverts commit fdc41e11f9687a50c97e2a59663bf2d541ff5489. It causes the libcxx/modules/stds_include.sh.cpp test to fail with: libcxx/include/ostream:1039:45: error: no template named 'enable_if_t'; did you mean 'enable_if'? template <class _Stream, class _Tp, class = enable_if_t<
Still investigating what's causing this and reverting in the meantime to get the bots green again.
|
 | libcxx/include/ostream |
 | libcxx/www/cxx2a_status.html |
 | libcxx/test/std/input.output/iostream.format/output.streams/ostream.rvalue/CharT_pointer.pass.cpp |
 | libcxx/include/istream |
 | libcxx/test/std/input.output/iostream.format/output.streams/ostream.rvalue/not_ostreamable.verify.cpp |
 | libcxx/test/std/input.output/iostream.format/input.streams/istream.rvalue/not_istreamable.verify.cpp |
 | libcxx/test/std/input.output/iostream.format/input.streams/istream.rvalue/rvalue.pass.cpp |
 | libcxx/test/std/input.output/iostream.format/output.streams/ostream.rvalue/rvalue.pass.cpp |
Commit
e077367a28102128483f4b2555d2ad31e21b1965
by david.sherwood[SVE] Make EVT::getScalarSizeInBits and others consistent with Type::getScalarSizeInBits
An existing function Type::getScalarSizeInBits returns a uint64_t instead of a TypeSize class because the caller is requesting a scalar size, which cannot be scalable. This patch makes other similar functions requesting a scalar size consistent with that, thereby eliminating more than 1000 implicit TypeSize -> uint64_t casts.
Differential revision: https://reviews.llvm.org/D87889
|
 | llvm/lib/Target/ARM/ARMISelLowering.cpp |
 | llvm/include/llvm/CodeGen/ValueTypes.h |
 | llvm/include/llvm/Support/MachineValueType.h |
 | llvm/lib/CodeGen/TargetLoweringBase.cpp |
 | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp |
 | llvm/include/llvm/CodeGen/SelectionDAGNodes.h |
 | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp |
 | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp |
Commit
d63a945a13048b66f06e222d8b0810d7db9592f6
by gabor.marton[analyzer][StdLibraryFunctionsChecker] Fix getline/getdelim signatures
It is no longer needed to add summaries of 'getline' for different possible underlying types of ssize_t. We can just simply lookup the type.
Differential Revision: https://reviews.llvm.org/D88092
|
 | clang/test/Analysis/std-c-library-functions.c |
 | clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp |
Commit
11d2e63ab0060c656398afd8ea26760031a9fb96
by gabor.marton[analyzer][StdLibraryFunctionsChecker] Separate the signature from the summaries
The signature should not be part of the summaries as many FIXME comments suggests. By separating the signature, we open up the way to a generic matching implementation which could be used later under the hoods of CallDescriptionMap.
Differential Revision: https://reviews.llvm.org/D88100
|
 | clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp |
Commit
310af42ed9ab259ad05ed46d459203b3473ba66e
by grimar[llvm-readelf/obj] - Cleanup the code. NFCI.
This: 1) Replaces pointers with references in many places. 2) Adds few TODOs about fixing possible unhandled errors (in ARMEHABIPrinter.h). 3) Replaces `auto`s with actual types. 4) Removes excessive arguments. 5) Adds `const ELFFile<ELFT> &Obj;` member to `ELFDumper` to simplify the code.
Differential revision: https://reviews.llvm.org/D88097
|
 | llvm/tools/llvm-readobj/ObjDumper.cpp |
 | llvm/tools/llvm-readobj/DwarfCFIEHPrinter.h |
 | llvm/tools/llvm-readobj/ObjDumper.h |
 | llvm/tools/llvm-readobj/llvm-readobj.cpp |
 | llvm/tools/llvm-readobj/ARMEHABIPrinter.h |
 | llvm/tools/llvm-readobj/ELFDumper.cpp |
Commit
ca907bfb57d8ad3ec3bcc2cff2abab7b1b933af6
by sebastian.neubauer[AMDGPU] Insert waitcnt after returning from call
When memory operations are outstanding on function calls, either the caller or the callee can insert a waitcnt to ensure that all reads are finished. Calls need some time to be executed, so if the callee inserts the waitcnt, filling the instruction buffer and waiting for memory will be interleaved, hiding some latency. This comes at the cost of having a waitcnt inside functions that may not be needed as no memory operations are outstanding.
For function calls, this is already implemented. The same principal applies to returns: If the caller inserts a waitcnt after the call, the callee does not have to wait and the return and memory operation can be run in parallel.
This commit implements waiting in the caller after returning from a function call.
Differential Revision: https://reviews.llvm.org/D87674
|
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll |
 | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll |
 | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.nogenerated.expected |
 | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll |
 | llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll |
 | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.buffer.ptr.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll |
 | llvm/test/CodeGen/AMDGPU/memcpy-fixed-align.ll |
 | llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.generated.expected |
 | llvm/test/CodeGen/AMDGPU/atomic_store_local.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll |
 | llvm/test/CodeGen/AMDGPU/atomic_load_local.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll |
 | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.dwordx3.ll |
 | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll |
 | llvm/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir |
 | llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll |
 | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.ll |
 | llvm/test/CodeGen/AMDGPU/load-lo16.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.ltolz.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll |
 | llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll |
 | llvm/test/CodeGen/AMDGPU/load-local.128.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll |
 | llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll |
 | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.getlod.dim.ll |
 | llvm/test/CodeGen/AMDGPU/lds-global-non-entry-func.ll |
 | llvm/test/CodeGen/AMDGPU/global-saddr-atomics.gfx1030.ll |
 | llvm/test/CodeGen/AMDGPU/call-waitcnt.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-non-entry-func.ll |
 | llvm/test/CodeGen/AMDGPU/load-local.96.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll |
 | llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll |
 | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.ll |
 | llvm/test/CodeGen/AMDGPU/function-args.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.fadd.ll |
 | llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll |
 | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/image_ls_mipmap_zero.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll |
 | llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll |
 | llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.fmax.ll |
 | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll |
 | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.ll |
 | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll |
 | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.ll |
 | llvm/test/CodeGen/AMDGPU/nested-calls.ll |
 | llvm/test/CodeGen/AMDGPU/imm16.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.fadd.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll |
 | llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll |
 | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll |
 | llvm/test/CodeGen/AMDGPU/shl.ll |
 | llvm/test/CodeGen/AMDGPU/ret_jump.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll |
 | llvm/test/CodeGen/AMDGPU/sibling-call.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll |
 | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll |
 | llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.fmin.ll |
 | llvm/test/CodeGen/AMDGPU/memory_clause.ll |
 | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll |
 | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/fmin_legacy.ll |
 | llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll |
 | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.ll |
 | llvm/test/CodeGen/AMDGPU/hsa-func.ll |
 | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll |
 | llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll |
 | llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll |
 | llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/fmax_legacy.ll |
 | llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll |
 | llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll |
 | llvm/test/CodeGen/AMDGPU/infer-uniform-load-shader.ll |
 | llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll |
 | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.ll |
 | llvm/test/CodeGen/AMDGPU/load-hi16.ll |
 | llvm/test/CodeGen/AMDGPU/stack-realign.ll |
 | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll |
 | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll |
 | llvm/test/CodeGen/AMDGPU/visit-physreg-vgpr-imm-folding-bug.ll |
 | llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll |
 | llvm/test/CodeGen/AMDGPU/offset-split-global.ll |
 | llvm/test/CodeGen/AMDGPU/store-hi16.ll |
 | llvm/test/CodeGen/AMDGPU/wave32.ll |
 | llvm/test/CodeGen/AMDGPU/call-argument-types.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll |
 | llvm/test/CodeGen/AMDGPU/global-saddr-load.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.ll |
 | llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.ltolz.a16.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll |
 | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll |
 | llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll |
 | llvm/test/CodeGen/AMDGPU/function-returns.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll |
 | llvm/test/CodeGen/AMDGPU/smrd.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll |
 | llvm/test/CodeGen/AMDGPU/offset-split-flat.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll |
 | llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll |
 | llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll |
Commit
d4035af2537432da41b2728829f8cd2fca9a9de8
by grimar[llvm-readelf/obj] - Print section symbol names properly when dumping relocations.
Currently `--relocations` ignores section symbol names and always prints section names for them. This is inconsistent with GNU readelf and with `--symbols`.
We have a code in `getFullSymbolName` (which is used for `--symbols`) which can be reused for `getRelocationTarget` (used for `--relocations`). With that the issue described is fixed and code becomes a bit shorter. Also with this change we start to print more relocations (in situations when we just showed warnings instead before) and also start to report more diagnostic warnings (see reloc-zero-name-or-value.test).
Differential revision: https://reviews.llvm.org/D87613
|
 | llvm/test/tools/llvm-readobj/ELF/section-symbols.test |
 | llvm/tools/llvm-readobj/ELFDumper.cpp |
 | llvm/test/tools/llvm-readobj/ELF/relocation-errors.test |
 | llvm/test/tools/llvm-readobj/ELF/reloc-zero-name-or-value.test |
 | llvm/test/tools/llvm-objcopy/ELF/Inputs/compress-debug-sections.yaml |
Commit
bd99fb4e0b5f2f3dcd8c9b81b30b4faebb765001
by grimar[llvm-readelf/obj] - Fix extended section symbol indices printed in warnings for MIPS GOT/PLT entries.
Recent refactoring introduced a symbol index argument for `getFullSymbolName` method, which is only used for reporting error messages about invalid extended symbol indexes.
There are few issues in the implementation and we don't report correct symbol indices when dumping MIPS GOT/PLT entries currently.
This patch adds test cases and fixes the issue.
Differential revision: https://reviews.llvm.org/D88089
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 | llvm/test/tools/llvm-readobj/ELF/mips-got.test |
 | llvm/test/tools/llvm-readobj/ELF/mips-plt.test |
 | llvm/tools/llvm-readobj/ELFDumper.cpp |
Commit
d0149ba9b46d6ca08b29c9a820b5cb772c799211
by kerry.mclaughlin[SVE][CodeGen] Lower legal integer -> floating point conversions
This patch adds new ISD nodes, SCVTZ_MERGE_PASSTHRU & UCVTZ_MERGE_PASSTHRU, which are used to lower both legal scalable vector [S|U]INT_TO_FP operations and the following intrinsics: - llvm.aarch64.sve.scvtf - llvm.aarch64.sve.ucvtf
Reviewed By: sdesmalen, efriedma
Differential Revision: https://reviews.llvm.org/D87913
|
 | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp |
 | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td |
 | llvm/lib/Target/AArch64/SVEInstrFormats.td |
 | llvm/lib/Target/AArch64/AArch64ISelLowering.h |
 | llvm/test/CodeGen/AArch64/sve-fcvt.ll |
Commit
bd72ed93d22a1579362859e64a0c7f9c68460cf8
by jperier[flang] CHARACTER(*) return does not require explicit interface
Fortran 2018 15.4.2.2(4)(c) says nonassumed or explicit non-constant length parameter require explicit interface. The "nonassumed" part was missing in f18 characteristic analysis causing CanBeCalledViaImplicitInterface to return false for `CHARACTER(*) function foo()` like interfaces.
Reviewed By: klausler
Differential Revision: https://reviews.llvm.org/D88075
|
 | flang/lib/Evaluate/characteristics.cpp |
Commit
301e23305d03cfb4004f845a1d9dfdc5e5931fd8
by Yaxun.Liu[CUDA][HIP] Fix static device var used by host code only
A static device variable may be accessed in host code through cudaMemCpyFromSymbol etc. Currently clang does not emit the static device variable if it is only referenced by host code, which causes host code to fail at run time.
This patch fixes that.
Differential Revision: https://reviews.llvm.org/D88115
|
 | clang/lib/CodeGen/CodeGenModule.cpp |
 | clang/test/CodeGenCUDA/static-device-var-no-rdc.cu |
Commit
34b08487f04a5a6621d94c17ef49e631cc187f4e
by SourabhSingh.Tomar[OpenMP][flang]Lower NUM_THREADS clause for parallel construct
This patch reflects the work that can be upstreamed from PR(merged) PR: https://github.com/flang-compiler/f18-llvm-project/pull/411
Reviewed By: jeanPerier
Differential Revision: https://reviews.llvm.org/D87846
|
 | flang/lib/Lower/OpenMP.cpp |
Commit
5711eaf608addccc5a23f0ea00630aa30280ea13
by limo[mlir] Added support for f64 memref printing in runner utils
Added print_memref_f64 function to runner utils.
Differential Revision: https://reviews.llvm.org/D88143
|
 | mlir/include/mlir/ExecutionEngine/RunnerUtils.h |
 | mlir/lib/ExecutionEngine/RunnerUtils.cpp |
Commit
be1197c403b22291e35cbc5e96788860ceabd40c
by SourabhSingh.Tomar[flang] Removed OpenMP lowering unittests
These tests aren't adding much value and consensus has been reached for there removal. For more context, please refer to discussion in this revision: https://reviews.llvm.org/D87846
|
 | flang/unittests/Lower/OpenMPLoweringTest.cpp |
 | flang/unittests/Lower/CMakeLists.txt |
 | flang/unittests/CMakeLists.txt |
Commit
dfa9065ad778fe830245e627c7fd9e39f2045bc9
by SourabhSingh.Tomar[NFCI][flang] Renamed a variable name to a more descriptive name
|
 | flang/lib/Lower/OpenMP.cpp |
Commit
c90dee1e90045feb039be640864f038eebd1d8cd
by Louis Dionne[libc++] Re-apply fdc41e11f (LWG1203) without breaking the C++11 build
fdc41e11f was reverted in e46c1def5 because it broke the C++11 build. We shouldn't be using enable_if_t in C++11, instead we must use enable_if<...>::type.
|
 | libcxx/include/ostream |
 | libcxx/test/std/input.output/iostream.format/output.streams/ostream.rvalue/rvalue.pass.cpp |
 | libcxx/test/std/input.output/iostream.format/output.streams/ostream.rvalue/not_ostreamable.verify.cpp |
 | libcxx/test/std/input.output/iostream.format/output.streams/ostream.rvalue/CharT_pointer.pass.cpp |
 | libcxx/www/cxx2a_status.html |
 | libcxx/include/istream |
 | libcxx/test/std/input.output/iostream.format/input.streams/istream.rvalue/not_istreamable.verify.cpp |
 | libcxx/test/std/input.output/iostream.format/input.streams/istream.rvalue/rvalue.pass.cpp |
Commit
20f84257ac4ac54ceb5f581a6081fac6eff2a5a1
by jotrem[lldb] Fix GetRemoteSharedModule fallback logic
When the various methods of locating the module in GetRemoteSharedModule fail, make sure we pass the original module spec to the bail-out call to the provided resolver function.
Also make sure we consistently use the resolved module spec from the various success paths.
Thanks to what appears to have been an accidentally inverted condition (commit 85967fa applied the new condition to a path where GetModuleSpec returns false, but should have applied it when GetModuleSpec returns true), without this fix we only pass the original module spec in the fallback if the original spec has no uuid (or has a uuid that somehow matches the resolved module's uuid despite the call to GetModuleSpec failing). This manifested as a bug when processing a minidump file with a user-provided sysroot, since in that case the resolver call was being applied to resolved_module_spec (despite resolution failing), which did not have the path of its file_spec set.
Reviewed By: JDevlieghere
Differential Revision: https://reviews.llvm.org/D88099
|
 | lldb/source/Target/Platform.cpp |
 | lldb/test/API/functionalities/postmortem/minidump-new/TestMiniDumpNew.py |
Commit
af0207f2bae8578c5283877a786e502ce6e33b14
by Matthew.ArsenaultAMDGPU: Check global FP atomics match default FP mode
We would always select global FP atomics from atomicrmw fadd, although they have a hardcoded FP mode.
|
 | llvm/lib/Target/AMDGPU/SIISelLowering.cpp |
 | llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll |
 | llvm/test/CodeGen/AMDGPU/global-atomics-fp.ll |
Commit
c463fd136ec259ec269ee6741763ce595811da71
by Matthew.ArsenaultGlobalISel: Fix truncating shift amount in trunc (shl) combine
The shift amount type does not necessarily match the result type. This was inserting a trunc from s32 to s32, which asserted. Just preserve the original shift amount type which can be legalized later.
|
 | llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shl.mir |
 | llvm/test/CodeGen/AArch64/GlobalISel/combine-trunc.mir |
Commit
1d1c382ed221f378fc866a524c7c673c239e94bc
by aaronFix typos in ASTMatchers.h; NFC
|
 | clang/include/clang/ASTMatchers/ASTMatchers.h |
 | clang/docs/LibASTMatchersReference.html |
Commit
00c34f72fba4b6b8a446d57e2257c27eedad1a1d
by sam.parker[NFC][ARM] Pre-commit tail predication test
|
 | llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir |
Commit
370a8c802558ed7aedbcc09c1bdf4c2d3f4c28c0
by paulsson[SystemZ] Make sure not to call getZExtValue on a >64 bit constant.
Better use isZero() and isIntN() in SystemZTargetTransformInfo rather than calling getZExtValue() since the immediate operand may be wider than 64 bits, which is not allowed with getZExtValue().
Fixes https://bugs.llvm.org/show_bug.cgi?id=47600
Review: Simon Pilgrim
|
 | llvm/test/Analysis/CostModel/SystemZ/huge-immediates.ll |
 | llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp |
Commit
9691806840606d48139b13516e9576902ba98923
by zinenko[mlir] Fix typos in Dialect.h. NFC.
|
 | mlir/include/mlir/IR/Dialect.h |
Commit
31923f6b360300b8b148ad257419766999dfe504
by flo[VPlan] Disconnect VPValue and VPUser.
This refactors VPuser to not inherit from VPValue to facilitate introducing operations that introduce multiple VPValues (e.g. VPInterleaveRecipe).
Reviewed By: Ayal
Differential Revision: https://reviews.llvm.org/D84679
|
 | llvm/lib/Transforms/Vectorize/VPlanSLP.cpp |
 | llvm/lib/Transforms/Vectorize/VPlan.h |
 | llvm/lib/Transforms/Vectorize/VPlanValue.h |
 | llvm/docs/Proposals/VectorizationPlan.rst |
Commit
db40a74344292410aa3e08c42834423013c4f192
by mcinally[SVE] Lower fixed length ISD::VECREDUCE_ADD to Scalable
Differential Revision: https://reviews.llvm.org/D87796
|
 | llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll |
 | llvm/lib/Target/AArch64/AArch64ISelLowering.h |
 | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp |
Commit
158af0d3d165c0382a6a291e81ffecf0b18ffe77
by usx[clangd] Refactor code completion signal's utility properties.
Current implementation of heuristic-based scoring function also contains computation of derived signals (e.g. whether name contains a word from context, computing file distances, scope distances.) This is an attempt to separate out the logic for computation of derived signals from the scoring function. This will allow us to have a clean API for scoring functions that will take only concrete code completion signals as input.
Differential Revision: https://reviews.llvm.org/D88146
|
 | clang-tools-extra/clangd/Quality.h |
 | clang-tools-extra/clangd/Quality.cpp |
Commit
270d334a665faa574db0c7d3a23af78bed9366d0
by paul[docs][llvm] Fix typos
I don't have commit access. Please help me commit it. Thanks : )
Reviewed By: Paul-C-Anagnostopoulos
Differential Revision: https://reviews.llvm.org/D88139
|
 | llvm/docs/TableGen/BackGuide.rst |
Commit
bd8b50cd7f5dd5237ec9187ef2fcea3adc15b61a
by clementval[mlir][openacc] Use OptionalParseResult in loop op parser instead of bool variables
This patch switch from using bool variables to OptionalParseResult for the parsing inside loop operation. This is already done for parallel operation and this patch unify this in the dialect.
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D88111
|
 | mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp |
Commit
7abb0ff7e0419a9554d77e9108cb7da670b7471c
by stellaraccidentAdd Operation to python bindings.
* Fixes a rather egregious bug with respect to the inability to return arbitrary objects from py::init (was causing aliasing of multiple py::object -> native instance). * Makes Modules and Operations referencable types so that they can be reliably depended on. * Uniques python operation instances within a context. Opens the door for further accounting. * Next I will retrofit region and block to be dependent on the operation, and I will attempt to model the API to avoid detached regions/blocks, which will simplify things a lot (in that world, only operations can be detached). * Added quite a bit of test coverage to check for leaks and reference issues. * Supercedes: https://reviews.llvm.org/D87213
Differential Revision: https://reviews.llvm.org/D87958
|
 | mlir/test/Bindings/Python/ir_attributes.py |
 | mlir/docs/Bindings/Python.md |
 | mlir/lib/Bindings/Python/IRModules.cpp |
 | mlir/test/Bindings/Python/ir_location.py |
 | mlir/test/Bindings/Python/ir_operation.py |
 | mlir/test/Bindings/Python/ir_types.py |
 | mlir/lib/Bindings/Python/IRModules.h |
 | mlir/test/Bindings/Python/ir_module.py |
Commit
4cf754c4bca94e957b634a854f57f4c7ec9151fb
by stellaraccidentImplement python iteration over the operation/region/block hierarchy.
* Removes the half-completed prior attempt at region/block mutation in favor of new approach to ownership. * Will re-add mutation more correctly in a follow-on. * Eliminates the detached state on blocks and regions, simplifying the ownership hierarchy. * Adds both iterator and index based access at each level.
Differential Revision: https://reviews.llvm.org/D87982
|
 | mlir/lib/CAPI/IR/IR.cpp |
 | mlir/test/Bindings/Python/ir_operation.py |
 | mlir/lib/Bindings/Python/IRModules.cpp |
 | mlir/lib/CAPI/IR/CMakeLists.txt |
 | mlir/include/mlir-c/IR.h |
 | mlir/lib/Bindings/Python/IRModules.h |
Commit
c1ded6a759913a32b44a851f0823bbb648d2a7e1
by stellaraccidentAdd mlir python APIs for creating operations, regions and blocks.
* The API is a bit more verbose than I feel like it needs to be. In a follow-up I'd like to abbreviate some things and look in to creating aliases for common accessors. * There is a lingering lifetime hazard between the module and newly added operations. We have the facilities now to solve for this but I will do that in a follow-up. * We may need to craft a more limited API for safely referencing successors when creating operations. We need more facilities to really prove that out and should defer for now.
Differential Revision: https://reviews.llvm.org/D87996
|
 | mlir/lib/Bindings/Python/PybindUtils.h |
 | mlir/lib/Bindings/Python/IRModules.cpp |
 | mlir/lib/Bindings/Python/IRModules.h |
 | mlir/test/Bindings/Python/ir_operation.py |
Commit
8e84972ab7060ace889bb383e76dc2c835a47c06
by stellaraccidentNFC: Remove unused variable.
|
 | mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp |