SuccessChanges

Summary

  1. AMDGPU/GlobalISel: Apply bitcast load/store hack to pointer vectors (details)
  2. [ARM][MVE] Tail-predication: remove the BTC + 1 overflow checks (details)
  3. AMDGPU/GlobalISel: Fix using unlegalizable values in tests (details)
  4. AMDGPU/GlobalISel: Use more accurate legality rules for merge/unmerge (details)
  5. [LiveDebugValues] Add switches for using instr-ref variable locations (details)
  6. [SelectionDAG] Legalize intrinsic get.active.lane.mask (details)
Commit ef8f3b5a78e9653917a5394a978cbc5ce7284a38 by Matthew.Arsenault
AMDGPU/GlobalISel: Apply bitcast load/store hack to pointer vectors

The selection patterns will currently fail on these.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir (diff)
Commit c352e7fbda2f48c285eca61d2509780f648443ee by sjoerd.meijer
[ARM][MVE] Tail-predication: remove the BTC + 1 overflow checks

This adapts tail-predication to the new semantics of get.active.lane.mask as
defined in D86147. This means that:
- we can remove the BTC + 1 overflow checks because now the loop tripcount is
  passed in to the intrinsic,
- we can immediately use that value to setup a counter for the number of
  elements processed by the loop and don't need to materialize BTC + 1.

Differential Revision: https://reviews.llvm.org/D86303
The file was modifiedllvm/test/CodeGen/Thumb2/mve-gather-scatter-tailpred.ll (diff)
The file was modifiedllvm/lib/Target/ARM/MVETailPredication.cpp (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-const.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-reduce.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/clear-maskedinsts.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-reduce-mve-tail.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-fma-loops.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-fabs.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-widen.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-round.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/extending-loads.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-add-sat.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/nested.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-sub-sat.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/basic-tail-pred.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll (diff)
Commit 984a499f9dff0fd16a6d4591970a58fabf966c4c by Matthew.Arsenault
AMDGPU/GlobalISel: Fix using unlegalizable values in tests

Implicit uses of non-register value types places impossible to satisfy
constraints on the legalizer / artifact combiner. These prevent
writing sensible legalize rules for the artifacts without triggering
infinite loops in the legalizer.

The verifier really needs to enforce this, but I'm not sure what the
exact conditions would look like yet.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir (diff)
Commit 0d2fe90063e956716c3067322aef898822d0dc0e by Matthew.Arsenault
AMDGPU/GlobalISel: Use more accurate legality rules for merge/unmerge

Most notably, we were incorrectly reporting <3 x s16> as a legal type
for these. Make sure these aren't legal to help make progress on
fixing the artifact combiner and vector legalizer
rules. Unfortunately, this means spreading the -global-isel-abort=0
hack, although this doesn't change the legalizer result in any
situation.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir (diff)
Commit 121a49d839d79f5a72be3e22a9d156c9e4b219dc by jeremy.morse
[LiveDebugValues] Add switches for using instr-ref variable locations

This patch adds the -Xclang option
"-fexperimental-debug-variable-locations" and same LLVM CodeGen option,
to pick which variable location tracking solution to use.

Right now all the switch does is pick which LiveDebugValues
implementation to use, the normal VarLoc one or the instruction
referencing one in rGae6f78824031. Over time, the aim is to add fragments
of support in aid of the value-tracking RFC:

  http://lists.llvm.org/pipermail/llvm-dev/2020-February/139440.html

also controlled by this command line switch. That will slowly move
variable locations to be defined by an instruction calculating a value,
and a DBG_INSTR_REF instruction referring to that value. Thus, this is
going to grow into a "use the new kind of variable locations" switch,
rather than just "use the new LiveDebugValues implementation".

Differential Revision: https://reviews.llvm.org/D83048
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp (diff)
The file was modifiedllvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp (diff)
The file was modifiedclang/include/clang/Basic/CodeGenOptions.def (diff)
The file was modifiedclang/include/clang/Driver/Options.td (diff)
The file was modifiedclang/lib/CodeGen/BackendUtil.cpp (diff)
The file was addedclang/test/Driver/debug-var-experimental-switch.c
The file was modifiedllvm/include/llvm/Target/TargetOptions.h (diff)
The file was modifiedllvm/include/llvm/CodeGen/CommandFlags.h (diff)
The file was modifiedllvm/lib/CodeGen/CommandFlags.cpp (diff)
Commit 39522b1e10428e4fa79a9d2dda20cbea7a1168e0 by sjoerd.meijer
[SelectionDAG] Legalize intrinsic get.active.lane.mask

This adapts legalization of intrinsic get.active.lane.mask to the new semantics
as described in D86147. Because the second argument is now the loop tripcount,
we legalize this intrinsic to an 'icmp ULT' instead of an ULE when it was the
backedge-taken count.

Differential Revision: https://reviews.llvm.org/D86302
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-round.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/active_lane_mask.ll (diff)